mirror of
https://github.com/AsahiLinux/u-boot
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401d1c4f5d
Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
229 lines
5.5 KiB
C
229 lines
5.5 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Google LLC
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* Written by Simon Glass <sjg@chromium.org>
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*/
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#include <common.h>
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#include <binman.h>
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#include <bootstage.h>
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#include <dm.h>
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#include <init.h>
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#include <irq.h>
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#include <log.h>
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#include <malloc.h>
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#include <p2sb.h>
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#include <acpi/acpi_s3.h>
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#include <asm/global_data.h>
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#include <asm/intel_pinctrl.h>
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#include <asm/io.h>
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#include <asm/intel_regs.h>
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#include <asm/msr.h>
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#include <asm/msr-index.h>
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#include <asm/pci.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/systemagent.h>
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#include <asm/arch/fsp_bindings.h>
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#include <asm/arch/fsp/fsp_configs.h>
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#include <asm/arch/fsp/fsp_s_upd.h>
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#include <dm/uclass-internal.h>
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#include <linux/bitops.h>
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#define PCH_P2SB_E0 0xe0
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#define HIDE_BIT BIT(0)
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int fsps_update_config(struct udevice *dev, ulong rom_offset,
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struct fsps_upd *upd)
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{
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struct fsp_s_config *cfg = &upd->config;
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ofnode node;
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if (IS_ENABLED(CONFIG_HAVE_VBT)) {
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void *buf;
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int ret;
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ret = binman_entry_map(ofnode_null(), "intel-vbt", &buf, NULL);
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if (ret)
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return log_msg_ret("Cannot find VBT", ret);
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if (*(u32 *)buf != VBT_SIGNATURE)
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return log_msg_ret("VBT signature", -EINVAL);
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/*
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* Load VBT before devicetree-specific config. This only
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* supports memory-mapped SPI at present.
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*/
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cfg->graphics_config_ptr = (ulong)buf;
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}
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node = dev_read_subnode(dev, "fsp-s");
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if (!ofnode_valid(node))
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return log_msg_ret("fsp-s settings", -ENOENT);
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return fsp_s_update_config_from_dtb(node, cfg);
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}
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/* Configure package power limits */
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static int set_power_limits(struct udevice *dev)
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{
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msr_t rapl_msr_reg, limit;
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u32 power_unit;
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u32 tdp, min_power, max_power;
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u32 pl2_val;
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u32 override_tdp[2];
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int ret;
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/* Get units */
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rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU_UNIT);
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power_unit = 1 << (rapl_msr_reg.lo & 0xf);
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/* Get power defaults for this SKU */
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rapl_msr_reg = msr_read(MSR_PKG_POWER_SKU);
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tdp = rapl_msr_reg.lo & PKG_POWER_LIMIT_MASK;
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pl2_val = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
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min_power = (rapl_msr_reg.lo >> 16) & PKG_POWER_LIMIT_MASK;
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max_power = rapl_msr_reg.hi & PKG_POWER_LIMIT_MASK;
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if (min_power > 0 && tdp < min_power)
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tdp = min_power;
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if (max_power > 0 && tdp > max_power)
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tdp = max_power;
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ret = dev_read_u32_array(dev, "tdp-pl-override-mw", override_tdp,
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ARRAY_SIZE(override_tdp));
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if (ret)
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return log_msg_ret("tdp-pl-override-mw", ret);
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/* Set PL1 override value */
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if (override_tdp[0])
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tdp = override_tdp[0] * power_unit / 1000;
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/* Set PL2 override value */
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if (override_tdp[1])
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pl2_val = override_tdp[1] * power_unit / 1000;
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/* Set long term power limit to TDP */
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limit.lo = tdp & PKG_POWER_LIMIT_MASK;
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/* Set PL1 Pkg Power clamp bit */
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limit.lo |= PKG_POWER_LIMIT_CLAMP;
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limit.lo |= PKG_POWER_LIMIT_EN;
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limit.lo |= (MB_POWER_LIMIT1_TIME_DEFAULT &
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PKG_POWER_LIMIT_TIME_MASK) << PKG_POWER_LIMIT_TIME_SHIFT;
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/* Set short term power limit PL2 */
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limit.hi = pl2_val & PKG_POWER_LIMIT_MASK;
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limit.hi |= PKG_POWER_LIMIT_EN;
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/* Program package power limits in RAPL MSR */
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msr_write(MSR_PKG_POWER_LIMIT, limit);
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log_debug("RAPL PL1 %d.%dW\n", tdp / power_unit,
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100 * (tdp % power_unit) / power_unit);
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log_debug("RAPL PL2 %d.%dW\n", pl2_val / power_unit,
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100 * (pl2_val % power_unit) / power_unit);
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/*
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* Sett RAPL MMIO register for Power limits. RAPL driver is using MSR
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* instead of MMIO, so disable LIMIT_EN bit for MMIO
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*/
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writel(limit.lo & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL));
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writel(limit.hi & ~PKG_POWER_LIMIT_EN, MCHBAR_REG(MCHBAR_RAPL_PPL + 4));
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return 0;
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}
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int p2sb_unhide(void)
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{
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struct udevice *dev;
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int ret;
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ret = uclass_find_first_device(UCLASS_P2SB, &dev);
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if (ret)
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return log_msg_ret("p2sb", ret);
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ret = p2sb_set_hide(dev, false);
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if (ret)
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return log_msg_ret("hide", ret);
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return 0;
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}
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/* Overwrites the SCI IRQ if another IRQ number is given by device tree */
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static void set_sci_irq(void)
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{
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/* Skip this for now */
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}
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int arch_fsps_preinit(void)
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{
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struct udevice *itss;
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int ret;
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if (!ll_boot_init())
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return 0;
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ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
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if (ret)
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return log_msg_ret("no itss", ret);
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/*
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* Clear the GPI interrupt status and enable registers. These
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* registers do not get reset to default state when booting from S5.
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*/
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ret = pinctrl_gpi_clear_int_cfg();
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if (ret)
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return log_msg_ret("gpi_clear", ret);
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return 0;
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}
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int arch_fsp_init_r(void)
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{
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bool s3wake;
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struct udevice *dev, *itss;
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int ret;
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if (!ll_boot_init())
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return 0;
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s3wake = IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) &&
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gd->arch.prev_sleep_state == ACPI_S3;
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/*
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* This must be called before any devices are probed. Put any probing
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* into arch_fsps_preinit() above.
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*
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* We don't use CONFIG_APL_BOOT_FROM_FAST_SPI_FLASH here since it will
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* force PCI to be probed.
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*/
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ret = fsp_silicon_init(s3wake, false);
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if (ret)
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return ret;
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ret = irq_first_device_type(X86_IRQT_ITSS, &itss);
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if (ret)
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return log_msg_ret("no itss", ret);
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/*
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* Restore GPIO IRQ polarities back to previous settings. This was
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* stored in reserve_arch() - see X86_IRQT_ITSS
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*/
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irq_restore_polarities(itss);
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/* soc_init() */
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ret = p2sb_unhide();
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if (ret)
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return log_msg_ret("unhide p2sb", ret);
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/* Set RAPL MSR for Package power limits*/
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ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
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if (ret)
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return log_msg_ret("Cannot get northbridge", ret);
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set_power_limits(dev);
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/*
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* FSP-S routes SCI to IRQ 9. With the help of this function you can
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* select another IRQ for SCI.
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*/
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set_sci_irq();
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return 0;
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}
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