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https://github.com/AsahiLinux/u-boot
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3b2979eefa
The definition of CONFIG_SPL_BOOTROM_SAVE is always a fixed CONFIG_SPL_STACK + 4, while CONFIG_SPL_STACK is not constant. This change will make it clear where the location is still, once CONFIG_SPL_STACK moves to Kconfig. Cc: Stefan Roese <sr@denx.de> Signed-off-by: Tom Rini <trini@konsulko.com>
84 lines
2 KiB
C
84 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
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*/
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#ifndef _CONFIG_THEADORABLE_H
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#define _CONFIG_THEADORABLE_H
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#include <linux/sizes.h>
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/*
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* High Level Configuration Options (easy to change)
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*/
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/*
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* TEXT_BASE needs to be below 16MiB, since this area is scrubbed
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* for DDR ECC byte filling in the SPL before loading the main
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* U-Boot into it.
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*/
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/*
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* The debugging version enables USB support via defconfig.
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* This version should also enable all other non-production
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* interfaces / features.
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*/
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/* I2C */
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#define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
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#define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE
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/* USB/EHCI configuration */
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#define CONFIG_USB_MAX_CONTROLLER_COUNT 3
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/* Environment in SPI NOR flash */
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#define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
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/* Keep device tree and initrd in lower memory so the kernel can access them */
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#define CONFIG_EXTRA_ENV_SETTINGS \
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"fdt_high=0x10000000\0" \
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"initrd_high=0x10000000\0"
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/* SATA support */
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#define CONFIG_LBA48
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/* FPGA programming support */
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#define CONFIG_FPGA_STRATIX_V
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/*
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* Bootcounter
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*/
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/* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */
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#define BOOTCOUNT_ADDR 0x1000
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/*
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* mv-common.h should be defined after CMD configs since it used them
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* to enable certain macros
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*/
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#include "mv-common.h"
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/*
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* Memory layout while starting into the bin_hdr via the
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* BootROM:
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*
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* 0x4000.4000 - 0x4003.4000 headers space (192KiB)
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* 0x4000.4030 bin_hdr start address
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* 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
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* 0x4007.fffc BootROM stack top
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*
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* The address space between 0x4007.fffc and 0x400f.fff is not locked in
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* L2 cache thus cannot be used.
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*/
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/* SPL */
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/* Defines for SPL */
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#define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
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#define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
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/* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
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#define CONFIG_SYS_SDRAM_SIZE SZ_2G
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#endif /* _CONFIG_THEADORABLE_H */
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