mirror of
https://github.com/AsahiLinux/u-boot
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3ad4472923
Signed-off-by: Gong Qianyu <Qianyu.Gong@freescale.com> Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com> Reviewed-by: York Sun <yorksun@freescale.com>
86 lines
3.3 KiB
Text
86 lines
3.3 KiB
Text
Overview
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--------
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The LS1043A Reference Design Board (RDB) is a high-performance computing,
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evaluation, and development platform that supports the QorIQ LS1043A
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LayerScape Architecture processor. The LS1043ARDB provides SW development
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platform for the Freescale LS1043A processor series, with a complete
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debugging environment. The LS1043A RDB is lead-free and RoHS-compliant.
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LS1043A SoC Overview
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--------------------
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The LS1043A integrated multicore processor combines four ARM Cortex-A53
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processor cores with datapath acceleration optimized for L2/3 packet
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processing, single pass security offload and robust traffic management
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and quality of service.
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The LS1043A SoC includes the following function and features:
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- Four 64-bit ARM Cortex-A53 CPUs
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- 1 MB unified L2 Cache
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- One 32-bit DDR3L/DDR4 SDRAM memory controllers with ECC and interleaving
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support
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- Data Path Acceleration Architecture (DPAA) incorporating acceleration the
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the following functions:
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- Packet parsing, classification, and distribution (FMan)
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- Queue management for scheduling, packet sequencing, and congestion
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management (QMan)
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- Hardware buffer management for buffer allocation and de-allocation (BMan)
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- Cryptography acceleration (SEC)
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- Ethernet interfaces by FMan
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- Up to 1 x XFI supporting 10G interface
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- Up to 1 x QSGMII
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- Up to 4 x SGMII supporting 1000Mbps
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- Up to 2 x SGMII supporting 2500Mbps
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- Up to 2 x RGMII supporting 1000Mbps
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- High-speed peripheral interfaces
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- Three PCIe 2.0 controllers, one supporting x4 operation
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- One serial ATA (SATA 3.0) controllers
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- Additional peripheral interfaces
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- Three high-speed USB 3.0 controllers with integrated PHY
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- Enhanced secure digital host controller (eSDXC/eMMC)
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- Quad Serial Peripheral Interface (QSPI) Controller
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- Serial peripheral interface (SPI) controller
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- Four I2C controllers
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- Two DUARTs
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- Integrated flash controller supporting NAND and NOR flash
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- QorIQ platform's trust architecture 2.1
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LS1043ARDB board Overview
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-----------------------
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- SERDES Connections, 4 lanes supporting:
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- PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and
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standard PCIe card
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- QSGMII with x4 RJ45 connector
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- XFI with x1 RJ45 connector
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- DDR Controller
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- 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s
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-IFC/Local Bus
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- One 128MB NOR flash 16-bit data bus
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- One 512 MB NAND flash with ECC support
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- CPLD connection
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- USB 3.0
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- Two super speed USB 3.0 Type A ports
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- SDHC: connects directly to a full SD/MMC slot
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- DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
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- 4 I2C controllers
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- UART
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- Two 4-pin serial ports at up to 115.2 Kbit/s
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- Two DB9 D-Type connectors supporting one Serial port each
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- ARM JTAG support
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Memory map from core's view
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----------------------------
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Start Address End Address Description Size
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0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB
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0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB
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0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB
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0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB
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0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB
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0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB
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0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB
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0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB
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0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB
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Booting Options
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---------------
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a) NOR boot
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b) NAND boot
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