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u-boot/arch/x86/cpu/ivybridge
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Simon Glass 3a5659f7cf x86: ivybridge: Drop support for ROM caching 
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)

Drop it.

Signed-off-by: Simon Glass <sjg@chromium.org>
2015-01-13 07:25:00 -08:00
..
bd82x6x.c x86: Add initial video device init for Intel GMA 2014-11-25 07:11:16 -07:00
car.S x86: chromebook_link: Implement CAR support (cache as RAM) 2014-11-21 07:34:11 +01:00
cpu.c x86: ivybridge: Drop support for ROM caching 2015-01-13 07:25:00 -08:00
early_init.c x86: ivybridge: Add early init for PCH devices 2014-11-21 07:34:14 +01:00
early_me.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
gma.c x86: ivybridge: Only run the Video BIOS when video is enabled 2015-01-13 07:24:59 -08:00
gma.h x86: Add initial video device init for Intel GMA 2014-11-25 07:11:16 -07:00
Kconfig x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
lpc.c x86: ivybridge: Add additional LPC init 2014-11-25 06:34:01 -07:00
Makefile x86: Add initial video device init for Intel GMA 2014-11-25 07:11:16 -07:00
me_status.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
microcode_intel.c x86: Correct problems in the microcode loading 2014-12-18 17:26:05 -07:00
model_206ax.c x86: Add init for model 206AX CPU 2014-11-25 06:34:14 -07:00
northbridge.c x86: ivybridge: Add northbridge init functions 2014-11-25 06:34:14 -07:00
pch.c x86: ivybridge: Add PCH init 2014-11-25 06:34:00 -07:00
pci.c x86: ivybridge: Add support for BD82x6x PCH 2014-11-25 06:34:00 -07:00
report_platform.c x86: ivybridge: Implement SDRAM init 2014-11-21 07:34:15 +01:00
sata.c x86: ivybridge: Add SATA init 2014-11-25 06:34:01 -07:00
sdram.c x86: Use consistent name XXX_ADDR for binary blob flash address 2014-12-18 17:26:07 -07:00
usb_ehci.c x86: ivybridge: Set up EHCI USB 2014-11-25 06:34:01 -07:00
usb_xhci.c x86: ivybridge: Set up XHCI USB 2014-11-25 06:34:02 -07:00