mirror of
https://github.com/AsahiLinux/u-boot
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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
61 lines
993 B
C
61 lines
993 B
C
// SPDX-License-Identifier: GPL-2.0+
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#include <common.h>
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#include <cpu_func.h>
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#include <asm/processor.h>
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#include <asm/system.h>
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#include <asm/io.h>
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#define WDT_BASE WTCNT
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#define WDT_WD (1 << 6)
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#define WDT_RST_P (0)
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#define WDT_RST_M (1 << 5)
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#define WDT_ENABLE (1 << 7)
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#if defined(CONFIG_WATCHDOG)
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static unsigned char csr_read(void)
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{
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return inb(WDT_BASE + 0x04);
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}
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static void cnt_write(unsigned char value)
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{
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outl((unsigned short)value | 0x5A00, WDT_BASE + 0x00);
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}
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static void csr_write(unsigned char value)
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{
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outl((unsigned short)value | 0xA500, WDT_BASE + 0x04);
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}
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void watchdog_reset(void)
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{
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outl(0x55000000, WDT_BASE + 0x08);
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}
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int watchdog_init(void)
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{
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/* Set overflow time*/
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cnt_write(0);
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/* Power on reset */
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csr_write(WDT_WD|WDT_RST_P|WDT_ENABLE);
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return 0;
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}
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int watchdog_disable(void)
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{
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csr_write(csr_read() & ~WDT_ENABLE);
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return 0;
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}
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#endif
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void reset_cpu(void)
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{
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/* Address error with SR.BL=1 first. */
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trigger_address_error();
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while (1)
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;
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}
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