mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-29 06:23:07 +00:00
dac1fa5c19
Some boards need to access GPIOs to determine which SDRAM is fitted to the board, for example chromebook_link. Probe this device (if it exists) to make sure that this works as expected. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
303 lines
6.7 KiB
C
303 lines
6.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (c) 2016 Google, Inc
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*/
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#define LOG_CATEGORY LOGC_BOOT
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#include <common.h>
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#include <cpu_func.h>
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#include <debug_uart.h>
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#include <dm.h>
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#include <hang.h>
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#include <image.h>
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#include <init.h>
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#include <irq_func.h>
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#include <log.h>
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#include <malloc.h>
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#include <spl.h>
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#include <syscon.h>
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#include <vesa.h>
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#include <asm/cpu.h>
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#include <asm/cpu_common.h>
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#include <asm/fsp2/fsp_api.h>
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#include <asm/global_data.h>
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#include <asm/mp.h>
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#include <asm/mrccache.h>
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#include <asm/mtrr.h>
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#include <asm/pci.h>
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#include <asm/processor.h>
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#include <asm/spl.h>
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#include <asm-generic/sections.h>
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DECLARE_GLOBAL_DATA_PTR;
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__weak int fsp_setup_pinctrl(void *ctx, struct event *event)
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{
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return 0;
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}
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#ifdef CONFIG_TPL
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static int set_max_freq(void)
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{
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if (cpu_get_burst_mode_state() == BURST_MODE_UNAVAILABLE) {
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/*
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* Burst Mode has been factory-configured as disabled and is not
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* available in this physical processor package
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*/
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debug("Burst Mode is factory-disabled\n");
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return -ENOENT;
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}
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/* Enable burst mode */
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cpu_set_burst_mode(true);
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/* Enable speed step */
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cpu_set_eist(true);
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/* Set P-State ratio */
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cpu_set_p_state_to_turbo_ratio();
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return 0;
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}
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#endif
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static int x86_spl_init(void)
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{
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struct udevice *dev;
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#ifndef CONFIG_TPL
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/*
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* TODO(sjg@chromium.org): We use this area of RAM for the stack
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* and global_data in SPL. Once U-Boot starts up and releocates it
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* is not needed. We could make this a CONFIG option or perhaps
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* place it immediately below CONFIG_TEXT_BASE.
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*/
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__maybe_unused char *ptr = (char *)0x110000;
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#else
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struct udevice *punit;
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#endif
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int ret;
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log_debug("x86 spl starting\n");
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if (IS_ENABLED(TPL))
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ret = x86_cpu_reinit_f();
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else
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ret = x86_cpu_init_f();
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ret = spl_init();
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if (ret) {
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log_debug("spl_init() failed (err=%d)\n", ret);
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return ret;
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}
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ret = arch_cpu_init();
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if (ret) {
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log_debug("arch_cpu_init() failed (err=%d)\n", ret);
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return ret;
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}
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#ifndef CONFIG_TPL
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ret = fsp_setup_pinctrl(NULL, NULL);
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if (ret) {
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log_debug("fsp_setup_pinctrl() failed (err=%d)\n", ret);
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return ret;
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}
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#endif
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/*
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* spl_board_init() below sets up the console if enabled. If it isn't,
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* do it here. We cannot call this twice since it results in a double
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* banner and CI tests fail.
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*/
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if (!IS_ENABLED(CONFIG_SPL_BOARD_INIT))
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preloader_console_init();
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#if !defined(CONFIG_TPL) && !CONFIG_IS_ENABLED(CPU)
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ret = print_cpuinfo();
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if (ret) {
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log_debug("print_cpuinfo() failed (err=%d)\n", ret);
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return ret;
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}
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#endif
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/* probe the LPC so we get the GPIO_BASE set up correctly */
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ret = uclass_first_device_err(UCLASS_LPC, &dev);
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if (ret && ret != -ENODEV) {
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log_debug("lpc probe failed\n");
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return ret;
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}
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ret = dram_init();
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if (ret) {
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log_debug("dram_init() failed (err=%d)\n", ret);
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return ret;
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}
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log_debug("mrc\n");
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if (IS_ENABLED(CONFIG_ENABLE_MRC_CACHE)) {
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ret = mrccache_spl_save();
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if (ret)
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log_debug("Failed to write to mrccache (err=%d)\n",
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ret);
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}
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#ifndef CONFIG_SYS_COREBOOT
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log_debug("bss\n");
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debug("BSS clear from %lx to %lx len %lx\n", (ulong)&__bss_start,
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(ulong)&__bss_end, (ulong)&__bss_end - (ulong)&__bss_start);
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memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start);
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# ifndef CONFIG_TPL
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/* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */
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ret = interrupt_init();
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if (ret) {
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debug("%s: interrupt_init() failed\n", __func__);
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return ret;
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}
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/*
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* The stack grows down from ptr. Put the global data at ptr. This
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* will only be used for SPL. Once SPL loads U-Boot proper it will
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* set up its own stack.
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*/
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gd->new_gd = (struct global_data *)ptr;
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memcpy(gd->new_gd, gd, sizeof(*gd));
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log_debug("logging\n");
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/*
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* Make sure logging is disabled when we switch, since the log system
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* list head will move
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*/
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gd->new_gd->flags &= ~GD_FLG_LOG_READY;
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arch_setup_gd(gd->new_gd);
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gd->start_addr_sp = (ulong)ptr;
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/* start up logging again, with the new list-head location */
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ret = log_init();
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if (ret) {
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log_debug("Log setup failed (err=%d)\n", ret);
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return ret;
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}
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if (_LOG_DEBUG) {
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ret = mtrr_list(mtrr_get_var_count(), MP_SELECT_BSP);
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if (ret)
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printf("mtrr_list failed\n");
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}
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/* Cache the SPI flash. Otherwise copying the code to RAM takes ages */
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ret = mtrr_add_request(MTRR_TYPE_WRBACK,
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(1ULL << 32) - CONFIG_XIP_ROM_SIZE,
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CONFIG_XIP_ROM_SIZE);
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if (ret) {
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debug("%s: SPI cache setup failed (err=%d)\n", __func__, ret);
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return ret;
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}
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# else
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ret = syscon_get_by_driver_data(X86_SYSCON_PUNIT, &punit);
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if (ret)
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debug("Could not find PUNIT (err=%d)\n", ret);
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ret = set_max_freq();
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if (ret)
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debug("Failed to set CPU frequency (err=%d)\n", ret);
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# endif
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#endif
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log_debug("done\n");
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return 0;
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}
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void board_init_f(ulong flags)
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{
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int ret;
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ret = x86_spl_init();
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if (ret) {
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printf("x86_spl_init: error %d\n", ret);
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hang();
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}
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#if IS_ENABLED(CONFIG_TPL) || IS_ENABLED(CONFIG_SYS_COREBOOT)
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gd->bd = malloc(sizeof(*gd->bd));
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if (!gd->bd) {
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printf("Out of memory for bd_info size %x\n", sizeof(*gd->bd));
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hang();
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}
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board_init_r(gd, 0);
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#else
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/* Uninit CAR and jump to board_init_f_r() */
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board_init_f_r_trampoline(gd->start_addr_sp);
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#endif
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}
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void board_init_f_r(void)
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{
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mtrr_commit(false);
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init_cache();
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gd->flags &= ~GD_FLG_SERIAL_READY;
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debug("cache status %d\n", dcache_status());
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board_init_r(gd, 0);
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}
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u32 spl_boot_device(void)
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{
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return BOOT_DEVICE_SPI_MMAP;
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}
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int spl_start_uboot(void)
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{
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return 0;
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}
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void spl_board_announce_boot_device(void)
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{
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printf("SPI flash");
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}
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static int spl_board_load_image(struct spl_image_info *spl_image,
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struct spl_boot_device *bootdev)
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{
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spl_image->size = CONFIG_SYS_MONITOR_LEN;
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spl_image->entry_point = CONFIG_TEXT_BASE;
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spl_image->load_addr = CONFIG_TEXT_BASE;
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spl_image->os = IH_OS_U_BOOT;
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spl_image->name = "U-Boot";
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if (!IS_ENABLED(CONFIG_SYS_COREBOOT)) {
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/* Copy U-Boot from ROM */
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memcpy((void *)spl_image->load_addr,
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(void *)spl_get_image_pos(), spl_get_image_size());
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}
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debug("Loading to %lx\n", spl_image->load_addr);
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return 0;
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}
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SPL_LOAD_IMAGE_METHOD("SPI", 5, BOOT_DEVICE_SPI_MMAP, spl_board_load_image);
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int spl_spi_load_image(void)
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{
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return -EPERM;
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}
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#ifdef CONFIG_X86_RUN_64BIT
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void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
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{
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int ret;
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printf("Jumping to 64-bit U-Boot: Note many features are missing\n");
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ret = cpu_jump_to_64bit_uboot(spl_image->entry_point);
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debug("ret=%d\n", ret);
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hang();
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}
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#endif
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void spl_board_init(void)
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{
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#ifndef CONFIG_TPL
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preloader_console_init();
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#endif
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if (CONFIG_IS_ENABLED(VIDEO)) {
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struct udevice *dev;
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/* Set up PCI video in SPL if required */
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uclass_first_device_err(UCLASS_PCI, &dev);
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uclass_first_device_err(UCLASS_VIDEO, &dev);
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}
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}
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