mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-24 03:53:31 +00:00
71d2a5e5ef
Synchronize R-Car device trees with Linux 6.1.7,
commit 21e996306a6afaae88295858de0ffb8955173a15 .
The following script has been used for the synchronization:
$ for i in $(cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) ; do
if [ -e /linux-2.6/arch/arm64/boot/dts/renesas/$i ] ; then
cp /linux-2.6/arch/arm64/boot/dts/renesas/$i arch/arm/dts/ ;
elif [ -e /linux-2.6/arch/arm/boot/dts/$i ] ; then
cp /linux-2.6/arch/arm/boot/dts/$i arch/arm/dts/
else
echo "NOT FOUND: $i"
fi
done
$ git add $( ( cd arch/arm/dts/ ; ls -1 r8a* | grep -v 'u-boot.dts' ; sed -n '/#include/ s@.*"\(.*\)"@\1@p' $(ls -1 r8a* | grep -v 'u-boot.dts')) | tr " " "\n" | sed 's@^@arch/arm/dts/@g' )
Move the include/dt-bindings/{clk,clock}/versaclock.h header used by
the renesas boards to match Linux 6.1.y as well.
Keep arch/arm/dts/r8a774c0-u-boot.dtsi sdhi3 node as it is now used
by the arch/arm/dts/r8a774c0-cat874.dts board.
Pick s@spi-flash@flash@ change in arch/arm/dts/r8a779a0-falcon-u-boot.dts
from "ARM: dts: Synchronize R-Car V3U DTs with Linux 5.18.3" .
Adjust R8A77990 Ebisu CONFIG_SYS_MMC_ENV_DEV from 2 to 0 to reflect
the card enumeration in ebisu.dtsi /aliases DT node .
Adjust R8A7795 and R8A7796 ULCB CONFIG_SYS_MMC_ENV_DEV from 1 to 0 to
reflect the card enumeration in ulcb.dtsi /aliases DT node .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> # r8a779a0-falcon-u-boot.dts
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> # r8a779a0-falcon-u-boot.dts
1473 lines
42 KiB
Text
1473 lines
42 KiB
Text
// SPDX-License-Identifier: GPL-2.0
|
|
/*
|
|
* Device Tree Source for the R-Car D3 (R8A77995) SoC
|
|
*
|
|
* Copyright (C) 2016 Renesas Electronics Corp.
|
|
* Copyright (C) 2017 Glider bvba
|
|
*/
|
|
|
|
#include <dt-bindings/clock/r8a77995-cpg-mssr.h>
|
|
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
|
#include <dt-bindings/power/r8a77995-sysc.h>
|
|
|
|
/ {
|
|
compatible = "renesas,r8a77995";
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
|
|
/*
|
|
* The external audio clocks are configured as 0 Hz fixed frequency
|
|
* clocks by default.
|
|
* Boards that provide audio clocks should override them.
|
|
*/
|
|
audio_clk_a: audio_clk_a {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
audio_clk_b: audio_clk_b {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
/* External CAN clock - to be overridden by boards that provide it */
|
|
can_clk: can {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
cpus {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
a53_0: cpu@0 {
|
|
compatible = "arm,cortex-a53";
|
|
reg = <0x0>;
|
|
device_type = "cpu";
|
|
power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
|
|
next-level-cache = <&L2_CA53>;
|
|
enable-method = "psci";
|
|
};
|
|
|
|
L2_CA53: cache-controller-1 {
|
|
compatible = "cache";
|
|
power-domains = <&sysc R8A77995_PD_CA53_SCU>;
|
|
cache-unified;
|
|
cache-level = <2>;
|
|
};
|
|
};
|
|
|
|
extal_clk: extal {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
/* This value must be overridden by the board */
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
pmu_a53 {
|
|
compatible = "arm,cortex-a53-pmu";
|
|
interrupts-extended = <&gic GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
psci {
|
|
compatible = "arm,psci-1.0", "arm,psci-0.2";
|
|
method = "smc";
|
|
};
|
|
|
|
scif_clk: scif {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <0>;
|
|
};
|
|
|
|
soc {
|
|
compatible = "simple-bus";
|
|
interrupt-parent = <&gic>;
|
|
#address-cells = <2>;
|
|
#size-cells = <2>;
|
|
ranges;
|
|
|
|
rwdt: watchdog@e6020000 {
|
|
compatible = "renesas,r8a77995-wdt",
|
|
"renesas,rcar-gen3-wdt";
|
|
reg = <0 0xe6020000 0 0x0c>;
|
|
interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 402>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 402>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpio0: gpio@e6050000 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6050000 0 0x50>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 0 9>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 912>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 912>;
|
|
};
|
|
|
|
gpio1: gpio@e6051000 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6051000 0 0x50>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 32 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 911>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 911>;
|
|
};
|
|
|
|
gpio2: gpio@e6052000 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6052000 0 0x50>;
|
|
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 64 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 910>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 910>;
|
|
};
|
|
|
|
gpio3: gpio@e6053000 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6053000 0 0x50>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 96 10>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 909>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 909>;
|
|
};
|
|
|
|
gpio4: gpio@e6054000 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6054000 0 0x50>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 128 32>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 908>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 908>;
|
|
};
|
|
|
|
gpio5: gpio@e6055000 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6055000 0 0x50>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 160 21>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 907>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 907>;
|
|
};
|
|
|
|
gpio6: gpio@e6055400 {
|
|
compatible = "renesas,gpio-r8a77995",
|
|
"renesas,rcar-gen3-gpio";
|
|
reg = <0 0xe6055400 0 0x50>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
#gpio-cells = <2>;
|
|
gpio-controller;
|
|
gpio-ranges = <&pfc 0 192 14>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
clocks = <&cpg CPG_MOD 906>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 906>;
|
|
};
|
|
|
|
pfc: pinctrl@e6060000 {
|
|
compatible = "renesas,pfc-r8a77995";
|
|
reg = <0 0xe6060000 0 0x508>;
|
|
};
|
|
|
|
cmt0: timer@e60f0000 {
|
|
compatible = "renesas,r8a77995-cmt0",
|
|
"renesas,rcar-gen3-cmt0";
|
|
reg = <0 0xe60f0000 0 0x1004>;
|
|
interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 303>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 303>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt1: timer@e6130000 {
|
|
compatible = "renesas,r8a77995-cmt1",
|
|
"renesas,rcar-gen3-cmt1";
|
|
reg = <0 0xe6130000 0 0x1004>;
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 302>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 302>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt2: timer@e6140000 {
|
|
compatible = "renesas,r8a77995-cmt1",
|
|
"renesas,rcar-gen3-cmt1";
|
|
reg = <0 0xe6140000 0 0x1004>;
|
|
interrupts = <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 301>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 301>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cmt3: timer@e6148000 {
|
|
compatible = "renesas,r8a77995-cmt1",
|
|
"renesas,rcar-gen3-cmt1";
|
|
reg = <0 0xe6148000 0 0x1004>;
|
|
interrupts = <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 300>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 300>;
|
|
status = "disabled";
|
|
};
|
|
|
|
cpg: clock-controller@e6150000 {
|
|
compatible = "renesas,r8a77995-cpg-mssr";
|
|
reg = <0 0xe6150000 0 0x1000>;
|
|
clocks = <&extal_clk>;
|
|
clock-names = "extal";
|
|
#clock-cells = <2>;
|
|
#power-domain-cells = <0>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
rst: reset-controller@e6160000 {
|
|
compatible = "renesas,r8a77995-rst";
|
|
reg = <0 0xe6160000 0 0x0200>;
|
|
};
|
|
|
|
sysc: system-controller@e6180000 {
|
|
compatible = "renesas,r8a77995-sysc";
|
|
reg = <0 0xe6180000 0 0x0400>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
thermal: thermal@e6190000 {
|
|
compatible = "renesas,thermal-r8a77995";
|
|
reg = <0 0xe6190000 0 0x10>, <0 0xe6190100 0 0x38>;
|
|
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 522>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 522>;
|
|
#thermal-sensor-cells = <0>;
|
|
};
|
|
|
|
intc_ex: interrupt-controller@e61c0000 {
|
|
compatible = "renesas,intc-ex-r8a77995", "renesas,irqc";
|
|
#interrupt-cells = <2>;
|
|
interrupt-controller;
|
|
reg = <0 0xe61c0000 0 0x200>;
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 407>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 407>;
|
|
};
|
|
|
|
tmu0: timer@e61e0000 {
|
|
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
|
reg = <0 0xe61e0000 0 0x30>;
|
|
interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 125>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 125>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu1: timer@e6fc0000 {
|
|
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
|
reg = <0 0xe6fc0000 0 0x30>;
|
|
interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 124>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 124>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu2: timer@e6fd0000 {
|
|
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
|
reg = <0 0xe6fd0000 0 0x30>;
|
|
interrupts = <GIC_SPI 303 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 123>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 123>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu3: timer@e6fe0000 {
|
|
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
|
reg = <0 0xe6fe0000 0 0x30>;
|
|
interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 122>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 122>;
|
|
status = "disabled";
|
|
};
|
|
|
|
tmu4: timer@ffc00000 {
|
|
compatible = "renesas,tmu-r8a77995", "renesas,tmu";
|
|
reg = <0 0xffc00000 0 0x30>;
|
|
interrupts = <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 121>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 121>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c0: i2c@e6500000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a77995",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe6500000 0 0x40>;
|
|
interrupts = <GIC_SPI 287 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 931>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 931>;
|
|
dmas = <&dmac1 0x91>, <&dmac1 0x90>,
|
|
<&dmac2 0x91>, <&dmac2 0x90>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@e6508000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a77995",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe6508000 0 0x40>;
|
|
interrupts = <GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 930>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 930>;
|
|
dmas = <&dmac1 0x93>, <&dmac1 0x92>,
|
|
<&dmac2 0x93>, <&dmac2 0x92>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@e6510000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a77995",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe6510000 0 0x40>;
|
|
interrupts = <GIC_SPI 286 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 929>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 929>;
|
|
dmas = <&dmac1 0x95>, <&dmac1 0x94>,
|
|
<&dmac2 0x95>, <&dmac2 0x94>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@e66d0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "renesas,i2c-r8a77995",
|
|
"renesas,rcar-gen3-i2c";
|
|
reg = <0 0xe66d0000 0 0x40>;
|
|
interrupts = <GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 928>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 928>;
|
|
dmas = <&dmac0 0x97>, <&dmac0 0x96>;
|
|
dma-names = "tx", "rx";
|
|
i2c-scl-internal-delay-ns = <6>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif0: serial@e6540000 {
|
|
compatible = "renesas,hscif-r8a77995",
|
|
"renesas,rcar-gen3-hscif",
|
|
"renesas,hscif";
|
|
reg = <0 0xe6540000 0 0x60>;
|
|
interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 520>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x31>, <&dmac1 0x30>,
|
|
<&dmac2 0x31>, <&dmac2 0x30>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 520>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hscif3: serial@e66a0000 {
|
|
compatible = "renesas,hscif-r8a77995",
|
|
"renesas,rcar-gen3-hscif",
|
|
"renesas,hscif";
|
|
reg = <0 0xe66a0000 0 0x60>;
|
|
interrupts = <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 517>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x37>, <&dmac0 0x36>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 517>;
|
|
status = "disabled";
|
|
};
|
|
|
|
hsusb: usb@e6590000 {
|
|
compatible = "renesas,usbhs-r8a77995",
|
|
"renesas,rcar-gen3-usbhs";
|
|
reg = <0 0xe6590000 0 0x200>;
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 704>, <&cpg CPG_MOD 703>;
|
|
dmas = <&usb_dmac0 0>, <&usb_dmac0 1>,
|
|
<&usb_dmac1 0>, <&usb_dmac1 1>;
|
|
dma-names = "ch0", "ch1", "ch2", "ch3";
|
|
renesas,buswait = <11>;
|
|
phys = <&usb2_phy0 3>;
|
|
phy-names = "usb";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 704>, <&cpg 703>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb_dmac0: dma-controller@e65a0000 {
|
|
compatible = "renesas,r8a77995-usb-dmac",
|
|
"renesas,usb-dmac";
|
|
reg = <0 0xe65a0000 0 0x100>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1";
|
|
clocks = <&cpg CPG_MOD 330>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 330>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <2>;
|
|
};
|
|
|
|
usb_dmac1: dma-controller@e65b0000 {
|
|
compatible = "renesas,r8a77995-usb-dmac",
|
|
"renesas,usb-dmac";
|
|
reg = <0 0xe65b0000 0 0x100>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1";
|
|
clocks = <&cpg CPG_MOD 331>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 331>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <2>;
|
|
};
|
|
|
|
arm_cc630p: crypto@e6601000 {
|
|
compatible = "arm,cryptocell-630p-ree";
|
|
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x0 0xe6601000 0 0x1000>;
|
|
clocks = <&cpg CPG_MOD 229>;
|
|
resets = <&cpg 229>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
};
|
|
|
|
canfd: can@e66c0000 {
|
|
compatible = "renesas,r8a77995-canfd",
|
|
"renesas,rcar-gen3-canfd";
|
|
reg = <0 0xe66c0000 0 0x8000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch_int", "g_int";
|
|
clocks = <&cpg CPG_MOD 914>,
|
|
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "fck", "canfd", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
|
assigned-clock-rates = <40000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 914>;
|
|
status = "disabled";
|
|
|
|
channel0 {
|
|
status = "disabled";
|
|
};
|
|
|
|
channel1 {
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
dmac0: dma-controller@e6700000 {
|
|
compatible = "renesas,dmac-r8a77995",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe6700000 0 0x10000>;
|
|
interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 219>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 219>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds0 0>, <&ipmmu_ds0 1>,
|
|
<&ipmmu_ds0 2>, <&ipmmu_ds0 3>,
|
|
<&ipmmu_ds0 4>, <&ipmmu_ds0 5>,
|
|
<&ipmmu_ds0 6>, <&ipmmu_ds0 7>;
|
|
};
|
|
|
|
dmac1: dma-controller@e7300000 {
|
|
compatible = "renesas,dmac-r8a77995",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7300000 0 0x10000>;
|
|
interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 217 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 219 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 218>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 218>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds1 0>, <&ipmmu_ds1 1>,
|
|
<&ipmmu_ds1 2>, <&ipmmu_ds1 3>,
|
|
<&ipmmu_ds1 4>, <&ipmmu_ds1 5>,
|
|
<&ipmmu_ds1 6>, <&ipmmu_ds1 7>;
|
|
};
|
|
|
|
dmac2: dma-controller@e7310000 {
|
|
compatible = "renesas,dmac-r8a77995",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xe7310000 0 0x10000>;
|
|
interrupts = <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7";
|
|
clocks = <&cpg CPG_MOD 217>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 217>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <8>;
|
|
iommus = <&ipmmu_ds1 16>, <&ipmmu_ds1 17>,
|
|
<&ipmmu_ds1 18>, <&ipmmu_ds1 19>,
|
|
<&ipmmu_ds1 20>, <&ipmmu_ds1 21>,
|
|
<&ipmmu_ds1 22>, <&ipmmu_ds1 23>;
|
|
};
|
|
|
|
ipmmu_ds0: iommu@e6740000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe6740000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 0>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_ds1: iommu@e7740000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe7740000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 1>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_hc: iommu@e6570000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe6570000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 2>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mm: iommu@e67b0000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xe67b0000 0 0x1000>;
|
|
interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_mp: iommu@ec670000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xec670000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 4>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_pv0: iommu@fd800000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfd800000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 6>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_rt: iommu@ffc80000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xffc80000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 10>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vc0: iommu@fe6b0000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfe6b0000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 12>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vi0: iommu@febd0000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfebd0000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 14>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
ipmmu_vp0: iommu@fe990000 {
|
|
compatible = "renesas,ipmmu-r8a77995";
|
|
reg = <0 0xfe990000 0 0x1000>;
|
|
renesas,ipmmu-main = <&ipmmu_mm 16>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
#iommu-cells = <1>;
|
|
};
|
|
|
|
avb: ethernet@e6800000 {
|
|
compatible = "renesas,etheravb-r8a77995",
|
|
"renesas,etheravb-rcar-gen3";
|
|
reg = <0 0xe6800000 0 0x800>;
|
|
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15",
|
|
"ch16", "ch17", "ch18", "ch19",
|
|
"ch20", "ch21", "ch22", "ch23",
|
|
"ch24";
|
|
clocks = <&cpg CPG_MOD 812>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 812>;
|
|
phy-mode = "rgmii";
|
|
rx-internal-delay-ps = <1800>;
|
|
iommus = <&ipmmu_ds0 16>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can0: can@e6c30000 {
|
|
compatible = "renesas,can-r8a77995",
|
|
"renesas,rcar-gen3-can";
|
|
reg = <0 0xe6c30000 0 0x1000>;
|
|
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 916>,
|
|
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
|
assigned-clock-rates = <40000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 916>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: can@e6c38000 {
|
|
compatible = "renesas,can-r8a77995",
|
|
"renesas,rcar-gen3-can";
|
|
reg = <0 0xe6c38000 0 0x1000>;
|
|
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 915>,
|
|
<&cpg CPG_CORE R8A77995_CLK_CANFD>,
|
|
<&can_clk>;
|
|
clock-names = "clkp1", "clkp2", "can_clk";
|
|
assigned-clocks = <&cpg CPG_CORE R8A77995_CLK_CANFD>;
|
|
assigned-clock-rates = <40000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 915>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm0: pwm@e6e30000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e30000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@e6e31000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e31000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@e6e32000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e32000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@e6e33000 {
|
|
compatible = "renesas,pwm-r8a77995", "renesas,pwm-rcar";
|
|
reg = <0 0xe6e33000 0 0x8>;
|
|
#pwm-cells = <2>;
|
|
clocks = <&cpg CPG_MOD 523>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 523>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif0: serial@e6e60000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e60000 0 64>;
|
|
interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 207>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x51>, <&dmac1 0x50>,
|
|
<&dmac2 0x51>, <&dmac2 0x50>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 207>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif1: serial@e6e68000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e68000 0 64>;
|
|
interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 206>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x53>, <&dmac1 0x52>,
|
|
<&dmac2 0x53>, <&dmac2 0x52>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 206>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif2: serial@e6e88000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6e88000 0 64>;
|
|
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 310>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x13>, <&dmac1 0x12>,
|
|
<&dmac2 0x13>, <&dmac2 0x12>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 310>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif3: serial@e6c50000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c50000 0 64>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 204>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x57>, <&dmac0 0x56>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 204>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif4: serial@e6c40000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6c40000 0 64>;
|
|
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 203>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac0 0x59>, <&dmac0 0x58>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 203>;
|
|
status = "disabled";
|
|
};
|
|
|
|
scif5: serial@e6f30000 {
|
|
compatible = "renesas,scif-r8a77995",
|
|
"renesas,rcar-gen3-scif", "renesas,scif";
|
|
reg = <0 0xe6f30000 0 64>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 202>,
|
|
<&cpg CPG_CORE R8A77995_CLK_S3D1C>,
|
|
<&scif_clk>;
|
|
clock-names = "fck", "brg_int", "scif_clk";
|
|
dmas = <&dmac1 0x5b>, <&dmac1 0x5a>,
|
|
<&dmac2 0x5b>, <&dmac2 0x5a>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 202>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof0: spi@e6e90000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6e90000 0 0x64>;
|
|
interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 211>;
|
|
dmas = <&dmac1 0x41>, <&dmac1 0x40>,
|
|
<&dmac2 0x41>, <&dmac2 0x40>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 211>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof1: spi@e6ea0000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6ea0000 0 0x64>;
|
|
interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 210>;
|
|
dmas = <&dmac1 0x43>, <&dmac1 0x42>,
|
|
<&dmac2 0x43>, <&dmac2 0x42>;
|
|
dma-names = "tx", "rx", "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 210>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof2: spi@e6c00000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c00000 0 0x64>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 209>;
|
|
dmas = <&dmac0 0x45>, <&dmac0 0x44>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 209>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
msiof3: spi@e6c10000 {
|
|
compatible = "renesas,msiof-r8a77995",
|
|
"renesas,rcar-gen3-msiof";
|
|
reg = <0 0xe6c10000 0 0x64>;
|
|
interrupts = <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 208>;
|
|
dmas = <&dmac0 0x47>, <&dmac0 0x46>;
|
|
dma-names = "tx", "rx";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 208>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
vin4: video@e6ef4000 {
|
|
compatible = "renesas,vin-r8a77995";
|
|
reg = <0 0xe6ef4000 0 0x1000>;
|
|
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 807>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 807>;
|
|
renesas,id = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rcar_sound: sound@ec500000 {
|
|
/*
|
|
* #sound-dai-cells is required
|
|
*
|
|
* Single DAI : #sound-dai-cells = <0>; <&rcar_sound>;
|
|
* Multi DAI : #sound-dai-cells = <1>; <&rcar_sound N>;
|
|
*/
|
|
/*
|
|
* #clock-cells is required for audio_clkout0/1/2/3
|
|
*
|
|
* clkout : #clock-cells = <0>; <&rcar_sound>;
|
|
* clkout0/1/2/3: #clock-cells = <1>; <&rcar_sound N>;
|
|
*/
|
|
compatible = "renesas,rcar_sound-r8a77995", "renesas,rcar_sound-gen3";
|
|
reg = <0 0xec500000 0 0x1000>, /* SCU */
|
|
<0 0xec5a0000 0 0x100>, /* ADG */
|
|
<0 0xec540000 0 0x1000>, /* SSIU */
|
|
<0 0xec541000 0 0x280>, /* SSI */
|
|
<0 0xec740000 0 0x200>; /* Audio DMAC peri peri*/
|
|
reg-names = "scu", "adg", "ssiu", "ssi", "audmapp";
|
|
|
|
clocks = <&cpg CPG_MOD 1005>,
|
|
<&cpg CPG_MOD 1011>, <&cpg CPG_MOD 1012>,
|
|
<&cpg CPG_MOD 1025>, <&cpg CPG_MOD 1026>,
|
|
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
|
<&cpg CPG_MOD 1020>, <&cpg CPG_MOD 1021>,
|
|
<&cpg CPG_MOD 1019>, <&cpg CPG_MOD 1018>,
|
|
<&audio_clk_a>, <&audio_clk_b>,
|
|
<&cpg CPG_CORE R8A77995_CLK_ZA2>;
|
|
clock-names = "ssi-all",
|
|
"ssi.4", "ssi.3",
|
|
"src.6", "src.5",
|
|
"mix.1", "mix.0",
|
|
"ctu.1", "ctu.0",
|
|
"dvc.0", "dvc.1",
|
|
"clk_a", "clk_b", "clk_i";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 1005>,
|
|
<&cpg 1011>, <&cpg 1012>;
|
|
reset-names = "ssi-all",
|
|
"ssi.4", "ssi.3";
|
|
status = "disabled";
|
|
|
|
rcar_sound,ctu {
|
|
ctu00: ctu-0 { };
|
|
ctu01: ctu-1 { };
|
|
ctu02: ctu-2 { };
|
|
ctu03: ctu-3 { };
|
|
ctu10: ctu-4 { };
|
|
ctu11: ctu-5 { };
|
|
ctu12: ctu-6 { };
|
|
ctu13: ctu-7 { };
|
|
};
|
|
|
|
rcar_sound,dvc {
|
|
dvc0: dvc-0 {
|
|
dmas = <&audma0 0xbc>;
|
|
dma-names = "tx";
|
|
};
|
|
dvc1: dvc-1 {
|
|
dmas = <&audma0 0xbe>;
|
|
dma-names = "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,mix {
|
|
mix0: mix-0 { };
|
|
mix1: mix-1 { };
|
|
};
|
|
|
|
rcar_sound,src {
|
|
src5: src-5 {
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x8f>, <&audma0 0xb2>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
src6: src-6 {
|
|
interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x91>, <&audma0 0xb4>;
|
|
dma-names = "rx", "tx";
|
|
};
|
|
};
|
|
|
|
rcar_sound,ssi {
|
|
ssi3: ssi-3 {
|
|
interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x07>, <&audma0 0x08>,
|
|
<&audma0 0x6f>, <&audma0 0x70>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
ssi4: ssi-4 {
|
|
interrupts = <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>;
|
|
dmas = <&audma0 0x09>, <&audma0 0x0a>,
|
|
<&audma0 0x71>, <&audma0 0x72>;
|
|
dma-names = "rx", "tx", "rxu", "txu";
|
|
};
|
|
};
|
|
};
|
|
|
|
mlp: mlp@ec520000 {
|
|
compatible = "renesas,r8a77995-mlp",
|
|
"renesas,rcar-gen3-mlp";
|
|
reg = <0 0xec520000 0 0x800>;
|
|
interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 385 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 802>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 802>;
|
|
status = "disabled";
|
|
};
|
|
|
|
audma0: dma-controller@ec700000 {
|
|
compatible = "renesas,dmac-r8a77995",
|
|
"renesas,rcar-dmac";
|
|
reg = <0 0xec700000 0 0x10000>;
|
|
interrupts = <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-names = "error",
|
|
"ch0", "ch1", "ch2", "ch3",
|
|
"ch4", "ch5", "ch6", "ch7",
|
|
"ch8", "ch9", "ch10", "ch11",
|
|
"ch12", "ch13", "ch14", "ch15";
|
|
clocks = <&cpg CPG_MOD 502>;
|
|
clock-names = "fck";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 502>;
|
|
#dma-cells = <1>;
|
|
dma-channels = <16>;
|
|
iommus = <&ipmmu_mp 0>, <&ipmmu_mp 1>,
|
|
<&ipmmu_mp 2>, <&ipmmu_mp 3>,
|
|
<&ipmmu_mp 4>, <&ipmmu_mp 5>,
|
|
<&ipmmu_mp 6>, <&ipmmu_mp 7>,
|
|
<&ipmmu_mp 8>, <&ipmmu_mp 9>,
|
|
<&ipmmu_mp 10>, <&ipmmu_mp 11>,
|
|
<&ipmmu_mp 12>, <&ipmmu_mp 13>,
|
|
<&ipmmu_mp 14>, <&ipmmu_mp 15>;
|
|
};
|
|
|
|
ohci0: usb@ee080000 {
|
|
compatible = "generic-ohci";
|
|
reg = <0 0xee080000 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
|
phys = <&usb2_phy0 1>;
|
|
phy-names = "usb";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>, <&cpg 704>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ehci0: usb@ee080100 {
|
|
compatible = "generic-ehci";
|
|
reg = <0 0xee080100 0 0x100>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
|
phys = <&usb2_phy0 2>;
|
|
phy-names = "usb";
|
|
companion = <&ohci0>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>, <&cpg 704>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usb2_phy0: usb-phy@ee080200 {
|
|
compatible = "renesas,usb2-phy-r8a77995",
|
|
"renesas,rcar-gen3-usb2-phy";
|
|
reg = <0 0xee080200 0 0x700>;
|
|
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 703>, <&cpg CPG_MOD 704>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 703>, <&cpg 704>;
|
|
#phy-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
sdhi2: mmc@ee140000 {
|
|
compatible = "renesas,sdhi-r8a77995",
|
|
"renesas,rcar-gen3-sdhi";
|
|
reg = <0 0xee140000 0 0x2000>;
|
|
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 312>, <&cpg CPG_CORE R8A77995_CLK_SD0H>;
|
|
clock-names = "core", "clkh";
|
|
max-frequency = <200000000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 312>;
|
|
iommus = <&ipmmu_ds1 34>;
|
|
status = "disabled";
|
|
};
|
|
|
|
rpc: spi@ee200000 {
|
|
compatible = "renesas,r8a77995-rpc-if",
|
|
"renesas,rcar-gen3-rpc-if";
|
|
reg = <0 0xee200000 0 0x200>,
|
|
<0 0x08000000 0 0x04000000>,
|
|
<0 0xee208000 0 0x100>;
|
|
reg-names = "regs", "dirmap", "wbuf";
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 917>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 917>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gic: interrupt-controller@f1010000 {
|
|
compatible = "arm,gic-400";
|
|
#interrupt-cells = <3>;
|
|
#address-cells = <0>;
|
|
interrupt-controller;
|
|
reg = <0x0 0xf1010000 0 0x1000>,
|
|
<0x0 0xf1020000 0 0x20000>,
|
|
<0x0 0xf1040000 0 0x20000>,
|
|
<0x0 0xf1060000 0 0x20000>;
|
|
interrupts = <GIC_PPI 9
|
|
(GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
|
|
clocks = <&cpg CPG_MOD 408>;
|
|
clock-names = "clk";
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 408>;
|
|
};
|
|
|
|
vspbs: vsp@fe960000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfe960000 0 0x8000>;
|
|
interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 627>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 627>;
|
|
renesas,fcp = <&fcpvb0>;
|
|
};
|
|
|
|
vspd0: vsp@fea20000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea20000 0 0x5000>;
|
|
interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 623>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 623>;
|
|
renesas,fcp = <&fcpvd0>;
|
|
};
|
|
|
|
vspd1: vsp@fea28000 {
|
|
compatible = "renesas,vsp2";
|
|
reg = <0 0xfea28000 0 0x5000>;
|
|
interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 622>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 622>;
|
|
renesas,fcp = <&fcpvd1>;
|
|
};
|
|
|
|
fcpvb0: fcp@fe96f000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfe96f000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 607>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 607>;
|
|
iommus = <&ipmmu_vp0 5>;
|
|
};
|
|
|
|
fcpvd0: fcp@fea27000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea27000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 603>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 603>;
|
|
iommus = <&ipmmu_vi0 8>;
|
|
};
|
|
|
|
fcpvd1: fcp@fea2f000 {
|
|
compatible = "renesas,fcpv";
|
|
reg = <0 0xfea2f000 0 0x200>;
|
|
clocks = <&cpg CPG_MOD 602>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 602>;
|
|
iommus = <&ipmmu_vi0 9>;
|
|
};
|
|
|
|
cmm0: cmm@fea40000 {
|
|
compatible = "renesas,r8a77995-cmm",
|
|
"renesas,rcar-gen3-cmm";
|
|
reg = <0 0xfea40000 0 0x1000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
clocks = <&cpg CPG_MOD 711>;
|
|
resets = <&cpg 711>;
|
|
};
|
|
|
|
cmm1: cmm@fea50000 {
|
|
compatible = "renesas,r8a77995-cmm",
|
|
"renesas,rcar-gen3-cmm";
|
|
reg = <0 0xfea50000 0 0x1000>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
clocks = <&cpg CPG_MOD 710>;
|
|
resets = <&cpg 710>;
|
|
};
|
|
|
|
du: display@feb00000 {
|
|
compatible = "renesas,du-r8a77995";
|
|
reg = <0 0xfeb00000 0 0x40000>;
|
|
interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
|
|
clock-names = "du.0", "du.1";
|
|
resets = <&cpg 724>;
|
|
reset-names = "du.0";
|
|
|
|
renesas,cmms = <&cmm0>, <&cmm1>;
|
|
renesas,vsps = <&vspd0 0>, <&vspd1 0>;
|
|
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
du_out_lvds0: endpoint {
|
|
remote-endpoint = <&lvds0_in>;
|
|
};
|
|
};
|
|
|
|
port@2 {
|
|
reg = <2>;
|
|
du_out_lvds1: endpoint {
|
|
remote-endpoint = <&lvds1_in>;
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds0: lvds-encoder@feb90000 {
|
|
compatible = "renesas,r8a77995-lvds";
|
|
reg = <0 0xfeb90000 0 0x20>;
|
|
clocks = <&cpg CPG_MOD 727>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 727>;
|
|
status = "disabled";
|
|
|
|
renesas,companion = <&lvds1>;
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
lvds0_in: endpoint {
|
|
remote-endpoint = <&du_out_lvds0>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
lvds1: lvds-encoder@feb90100 {
|
|
compatible = "renesas,r8a77995-lvds";
|
|
reg = <0 0xfeb90100 0 0x20>;
|
|
clocks = <&cpg CPG_MOD 727>;
|
|
power-domains = <&sysc R8A77995_PD_ALWAYS_ON>;
|
|
resets = <&cpg 726>;
|
|
status = "disabled";
|
|
|
|
ports {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
port@0 {
|
|
reg = <0>;
|
|
lvds1_in: endpoint {
|
|
remote-endpoint = <&du_out_lvds1>;
|
|
};
|
|
};
|
|
|
|
port@1 {
|
|
reg = <1>;
|
|
};
|
|
};
|
|
};
|
|
|
|
prr: chipid@fff00044 {
|
|
compatible = "renesas,prr";
|
|
reg = <0 0xfff00044 0 4>;
|
|
};
|
|
};
|
|
|
|
thermal-zones {
|
|
cpu_thermal: cpu-thermal {
|
|
polling-delay-passive = <250>;
|
|
polling-delay = <1000>;
|
|
thermal-sensors = <&thermal>;
|
|
|
|
cooling-maps {
|
|
};
|
|
|
|
trips {
|
|
cpu-crit {
|
|
temperature = <120000>;
|
|
hysteresis = <2000>;
|
|
type = "critical";
|
|
};
|
|
};
|
|
};
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<&gic GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
};
|