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https://github.com/AsahiLinux/u-boot
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395f12976c
For DK1/DK2 boards, check if power supply provides enough current to allow the board to boot correctly. ADC@0 channel 18 and 19 are connected to USB type-C CC1 and CC2 signals. The table below shows the behavior for different range of CC1 or CC2: range | power supply | red led | console message (Volts) | (Amps) | blinks | --------------|--------------|---------|----------------------------------- [2.10 - 1.23[ | 3 | NO | NO [1.23 - 0.66[ | 1.5 | 3 times | WARNING 1.5A power supply detected [0.66 - 0] | 0.5 | 2 times | WARNING 500mA power supply detected If detected current is < 3A, red led is kept ON after blinking. Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
584 lines
14 KiB
C
584 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
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/*
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* Copyright (C) 2018, STMicroelectronics - All Rights Reserved
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*/
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#include <common.h>
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#include <adc.h>
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#include <config.h>
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#include <clk.h>
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#include <dm.h>
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#include <generic-phy.h>
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#include <led.h>
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#include <misc.h>
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#include <phy.h>
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#include <reset.h>
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#include <syscon.h>
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#include <usb.h>
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#include <asm/io.h>
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#include <asm/gpio.h>
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#include <asm/arch/stm32.h>
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#include <power/regulator.h>
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#include <usb/dwc2_udc.h>
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/* SYSCFG registers */
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#define SYSCFG_BOOTR 0x00
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#define SYSCFG_PMCSETR 0x04
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#define SYSCFG_IOCTRLSETR 0x18
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#define SYSCFG_ICNR 0x1C
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#define SYSCFG_CMPCR 0x20
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#define SYSCFG_CMPENSETR 0x24
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#define SYSCFG_PMCCLRR 0x44
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#define SYSCFG_BOOTR_BOOT_MASK GENMASK(2, 0)
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#define SYSCFG_BOOTR_BOOTPD_SHIFT 4
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#define SYSCFG_IOCTRLSETR_HSLVEN_TRACE BIT(0)
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#define SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI BIT(1)
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#define SYSCFG_IOCTRLSETR_HSLVEN_ETH BIT(2)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SDMMC BIT(3)
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#define SYSCFG_IOCTRLSETR_HSLVEN_SPI BIT(4)
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#define SYSCFG_CMPCR_SW_CTRL BIT(1)
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#define SYSCFG_CMPCR_READY BIT(8)
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#define SYSCFG_CMPENSETR_MPU_EN BIT(0)
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#define SYSCFG_PMCSETR_ETH_CLK_SEL BIT(16)
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#define SYSCFG_PMCSETR_ETH_REF_CLK_SEL BIT(17)
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#define SYSCFG_PMCSETR_ETH_SELMII BIT(20)
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#define SYSCFG_PMCSETR_ETH_SEL_MASK GENMASK(23, 21)
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#define SYSCFG_PMCSETR_ETH_SEL_GMII_MII (0 << 21)
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#define SYSCFG_PMCSETR_ETH_SEL_RGMII (1 << 21)
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#define SYSCFG_PMCSETR_ETH_SEL_RMII (4 << 21)
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/*
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* Get a global data pointer
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*/
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DECLARE_GLOBAL_DATA_PTR;
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#define STM32MP_GUSBCFG 0x40002407
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#define STM32MP_GGPIO 0x38
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#define STM32MP_GGPIO_VBUS_SENSING BIT(21)
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#define USB_WARNING_LOW_THRESHOLD_UV 660000
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#define USB_START_LOW_THRESHOLD_UV 1230000
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#define USB_START_HIGH_THRESHOLD_UV 2100000
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int checkboard(void)
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{
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int ret;
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char *mode;
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u32 otp;
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struct udevice *dev;
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const char *fdt_compat;
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int fdt_compat_len;
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if (IS_ENABLED(CONFIG_STM32MP1_TRUSTED))
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mode = "trusted";
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else
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mode = "basic";
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printf("Board: stm32mp1 in %s mode", mode);
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fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
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&fdt_compat_len);
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if (fdt_compat && fdt_compat_len)
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printf(" (%s)", fdt_compat);
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puts("\n");
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ret = uclass_get_device_by_driver(UCLASS_MISC,
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DM_GET_DRIVER(stm32mp_bsec),
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&dev);
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if (!ret)
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ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_BOARD),
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&otp, sizeof(otp));
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if (!ret && otp) {
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printf("Board: MB%04x Var%d Rev.%c-%02d\n",
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otp >> 16,
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(otp >> 12) & 0xF,
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((otp >> 8) & 0xF) - 1 + 'A',
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otp & 0xF);
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}
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return 0;
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}
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static void board_key_check(void)
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{
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#if defined(CONFIG_FASTBOOT) || defined(CONFIG_CMD_STM32PROG)
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ofnode node;
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struct gpio_desc gpio;
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enum forced_boot_mode boot_mode = BOOT_NORMAL;
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return;
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}
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#ifdef CONFIG_FASTBOOT
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if (gpio_request_by_name_nodev(node, "st,fastboot-gpios", 0,
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&gpio, GPIOD_IS_IN)) {
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debug("%s: could not find a /config/st,fastboot-gpios\n",
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__func__);
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} else {
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if (dm_gpio_get_value(&gpio)) {
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puts("Fastboot key pressed, ");
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boot_mode = BOOT_FASTBOOT;
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}
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dm_gpio_free(NULL, &gpio);
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}
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#endif
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#ifdef CONFIG_CMD_STM32PROG
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if (gpio_request_by_name_nodev(node, "st,stm32prog-gpios", 0,
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&gpio, GPIOD_IS_IN)) {
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debug("%s: could not find a /config/st,stm32prog-gpios\n",
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__func__);
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} else {
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if (dm_gpio_get_value(&gpio)) {
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puts("STM32Programmer key pressed, ");
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boot_mode = BOOT_STM32PROG;
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}
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dm_gpio_free(NULL, &gpio);
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}
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#endif
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if (boot_mode != BOOT_NORMAL) {
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puts("entering download mode...\n");
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clrsetbits_le32(TAMP_BOOT_CONTEXT,
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TAMP_BOOT_FORCED_MASK,
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boot_mode);
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}
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#endif
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}
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static struct dwc2_plat_otg_data stm32mp_otg_data = {
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.usb_gusbcfg = STM32MP_GUSBCFG,
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};
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static struct reset_ctl usbotg_reset;
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int board_usb_init(int index, enum usb_init_type init)
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{
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struct fdtdec_phandle_args args;
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struct udevice *dev;
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const void *blob = gd->fdt_blob;
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struct clk clk;
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struct phy phy;
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int node;
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int phy_provider;
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int ret;
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/* find the usb otg node */
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node = fdt_node_offset_by_compatible(blob, -1, "snps,dwc2");
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if (node < 0) {
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debug("Not found usb_otg device\n");
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return -ENODEV;
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}
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if (!fdtdec_get_is_enabled(blob, node)) {
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debug("stm32 usbotg is disabled in the device tree\n");
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return -ENODEV;
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}
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/* Enable clock */
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ret = fdtdec_parse_phandle_with_args(blob, node, "clocks",
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"#clock-cells", 0, 0, &args);
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if (ret) {
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debug("usbotg has no clocks defined in the device tree\n");
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return ret;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_CLK, args.node, &dev);
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if (ret)
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return ret;
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if (args.args_count != 1) {
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debug("Can't find clock ID in the device tree\n");
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return -ENODATA;
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}
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clk.dev = dev;
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clk.id = args.args[0];
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ret = clk_enable(&clk);
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if (ret) {
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debug("Failed to enable usbotg clock\n");
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return ret;
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}
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/* Reset */
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ret = fdtdec_parse_phandle_with_args(blob, node, "resets",
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"#reset-cells", 0, 0, &args);
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if (ret) {
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debug("usbotg has no resets defined in the device tree\n");
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goto clk_err;
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}
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ret = uclass_get_device_by_of_offset(UCLASS_RESET, args.node, &dev);
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if (ret || args.args_count != 1)
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goto clk_err;
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usbotg_reset.dev = dev;
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usbotg_reset.id = args.args[0];
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reset_assert(&usbotg_reset);
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udelay(2);
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reset_deassert(&usbotg_reset);
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/* Get USB PHY */
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ret = fdtdec_parse_phandle_with_args(blob, node, "phys",
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"#phy-cells", 0, 0, &args);
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if (!ret) {
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phy_provider = fdt_parent_offset(blob, args.node);
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ret = uclass_get_device_by_of_offset(UCLASS_PHY,
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phy_provider, &dev);
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if (ret)
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goto clk_err;
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phy.dev = dev;
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phy.id = fdtdec_get_uint(blob, args.node, "reg", -1);
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ret = generic_phy_power_on(&phy);
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if (ret) {
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debug("unable to power on the phy\n");
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goto clk_err;
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}
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ret = generic_phy_init(&phy);
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if (ret) {
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debug("failed to init usb phy\n");
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goto phy_power_err;
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}
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}
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/* Parse and store data needed for gadget */
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stm32mp_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg");
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if (stm32mp_otg_data.regs_otg == FDT_ADDR_T_NONE) {
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debug("usbotg: can't get base address\n");
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ret = -ENODATA;
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goto phy_init_err;
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}
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stm32mp_otg_data.rx_fifo_sz = fdtdec_get_int(blob, node,
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"g-rx-fifo-size", 0);
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stm32mp_otg_data.np_tx_fifo_sz = fdtdec_get_int(blob, node,
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"g-np-tx-fifo-size", 0);
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stm32mp_otg_data.tx_fifo_sz = fdtdec_get_int(blob, node,
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"g-tx-fifo-size", 0);
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/* Enable voltage level detector */
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if (!(fdtdec_parse_phandle_with_args(blob, node, "usb33d-supply",
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NULL, 0, 0, &args))) {
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if (!uclass_get_device_by_of_offset(UCLASS_REGULATOR,
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args.node, &dev)) {
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ret = regulator_set_enable(dev, true);
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if (ret) {
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debug("Failed to enable usb33d\n");
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goto phy_init_err;
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}
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}
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}
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/* Enable vbus sensing */
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setbits_le32(stm32mp_otg_data.regs_otg + STM32MP_GGPIO,
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STM32MP_GGPIO_VBUS_SENSING);
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return dwc2_udc_probe(&stm32mp_otg_data);
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phy_init_err:
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generic_phy_exit(&phy);
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phy_power_err:
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generic_phy_power_off(&phy);
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clk_err:
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clk_disable(&clk);
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return ret;
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}
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static int get_led(struct udevice **dev, char *led_string)
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{
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char *led_name;
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int ret;
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led_name = fdtdec_get_config_string(gd->fdt_blob, led_string);
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if (!led_name) {
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pr_debug("%s: could not find %s config string\n",
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__func__, led_string);
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return -ENOENT;
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}
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ret = led_get_by_label(led_name, dev);
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if (ret) {
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debug("%s: get=%d\n", __func__, ret);
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return ret;
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}
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return 0;
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}
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static int setup_led(enum led_state_t cmd)
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{
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struct udevice *dev;
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int ret;
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ret = get_led(&dev, "u-boot,boot-led");
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if (ret)
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return ret;
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ret = led_set_state(dev, cmd);
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return ret;
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}
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static int board_check_usb_power(void)
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{
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struct ofnode_phandle_args adc_args;
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struct udevice *adc;
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struct udevice *led;
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ofnode node;
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unsigned int raw;
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int max_uV = 0;
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int ret, uV, adc_count;
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u8 i, nb_blink;
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node = ofnode_path("/config");
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if (!ofnode_valid(node)) {
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debug("%s: no /config node?\n", __func__);
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return -ENOENT;
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}
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/*
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* Retrieve the ADC channels devices and get measurement
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* for each of them
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*/
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adc_count = ofnode_count_phandle_with_args(node, "st,adc_usb_pd",
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"#io-channel-cells");
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if (adc_count < 0) {
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if (adc_count == -ENOENT)
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return 0;
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pr_err("%s: can't find adc channel (%d)\n", __func__,
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adc_count);
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return adc_count;
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}
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for (i = 0; i < adc_count; i++) {
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if (ofnode_parse_phandle_with_args(node, "st,adc_usb_pd",
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"#io-channel-cells", 0, i,
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&adc_args)) {
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pr_debug("%s: can't find /config/st,adc_usb_pd\n",
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__func__);
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return 0;
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}
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ret = uclass_get_device_by_ofnode(UCLASS_ADC, adc_args.node,
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&adc);
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if (ret) {
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pr_err("%s: Can't get adc device(%d)\n", __func__,
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ret);
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return ret;
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}
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ret = adc_channel_single_shot(adc->name, adc_args.args[0],
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&raw);
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if (ret) {
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pr_err("%s: single shot failed for %s[%d]!\n",
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__func__, adc->name, adc_args.args[0]);
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return ret;
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}
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/* Convert to uV */
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if (!adc_raw_to_uV(adc, raw, &uV)) {
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if (uV > max_uV)
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max_uV = uV;
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pr_debug("%s: %s[%02d] = %u, %d uV\n", __func__,
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adc->name, adc_args.args[0], raw, uV);
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} else {
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pr_err("%s: Can't get uV value for %s[%d]\n",
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__func__, adc->name, adc_args.args[0]);
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}
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}
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/*
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* If highest value is inside 1.23 Volts and 2.10 Volts, that means
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* board is plugged on an USB-C 3A power supply and boot process can
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* continue.
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*/
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if (max_uV > USB_START_LOW_THRESHOLD_UV &&
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max_uV < USB_START_HIGH_THRESHOLD_UV)
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return 0;
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/* Display warning message and make u-boot,error-led blinking */
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pr_err("\n*******************************************\n");
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if (max_uV < USB_WARNING_LOW_THRESHOLD_UV) {
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pr_err("* WARNING 500mA power supply detected *\n");
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nb_blink = 2;
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} else {
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pr_err("* WARNING 1.5A power supply detected *\n");
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nb_blink = 3;
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}
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pr_err("* Current too low, use a 3A power supply! *\n");
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pr_err("*******************************************\n\n");
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ret = get_led(&led, "u-boot,error-led");
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if (ret)
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return ret;
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for (i = 0; i < nb_blink * 2; i++) {
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led_set_state(led, LEDST_TOGGLE);
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mdelay(125);
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}
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led_set_state(led, LEDST_ON);
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return 0;
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}
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int board_usb_cleanup(int index, enum usb_init_type init)
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{
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/* Reset usbotg */
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reset_assert(&usbotg_reset);
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udelay(2);
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reset_deassert(&usbotg_reset);
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return 0;
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}
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static void sysconf_init(void)
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{
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#ifndef CONFIG_STM32MP1_TRUSTED
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u8 *syscfg;
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#ifdef CONFIG_DM_REGULATOR
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struct udevice *pwr_dev;
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struct udevice *pwr_reg;
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struct udevice *dev;
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int ret;
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u32 otp = 0;
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#endif
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u32 bootr;
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syscfg = (u8 *)syscon_get_first_range(STM32MP_SYSCON_SYSCFG);
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/* interconnect update : select master using the port 1 */
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/* LTDC = AXI_M9 */
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/* GPU = AXI_M8 */
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/* today information is hardcoded in U-Boot */
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writel(BIT(9), syscfg + SYSCFG_ICNR);
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/* disable Pull-Down for boot pin connected to VDD */
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bootr = readl(syscfg + SYSCFG_BOOTR);
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bootr &= ~(SYSCFG_BOOTR_BOOT_MASK << SYSCFG_BOOTR_BOOTPD_SHIFT);
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bootr |= (bootr & SYSCFG_BOOTR_BOOT_MASK) << SYSCFG_BOOTR_BOOTPD_SHIFT;
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writel(bootr, syscfg + SYSCFG_BOOTR);
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#ifdef CONFIG_DM_REGULATOR
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/* High Speed Low Voltage Pad mode Enable for SPI, SDMMC, ETH, QSPI
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* and TRACE. Needed above ~50MHz and conditioned by AFMUX selection.
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* The customer will have to disable this for low frequencies
|
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* or if AFMUX is selected but the function not used, typically for
|
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* TRACE. Otherwise, impact on power consumption.
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*
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* WARNING:
|
|
* enabling High Speed mode while VDD>2.7V
|
|
* with the OTP product_below_2v5 (OTP 18, BIT 13)
|
|
* erroneously set to 1 can damage the IC!
|
|
* => U-Boot set the register only if VDD < 2.7V (in DT)
|
|
* but this value need to be consistent with board design
|
|
*/
|
|
ret = syscon_get_by_driver_data(STM32MP_SYSCON_PWR, &pwr_dev);
|
|
if (!ret) {
|
|
ret = uclass_get_device_by_driver(UCLASS_MISC,
|
|
DM_GET_DRIVER(stm32mp_bsec),
|
|
&dev);
|
|
if (ret) {
|
|
pr_err("Can't find stm32mp_bsec driver\n");
|
|
return;
|
|
}
|
|
|
|
ret = misc_read(dev, STM32_BSEC_SHADOW(18), &otp, 4);
|
|
if (!ret)
|
|
otp = otp & BIT(13);
|
|
|
|
/* get VDD = pwr-supply */
|
|
ret = device_get_supply_regulator(pwr_dev, "pwr-supply",
|
|
&pwr_reg);
|
|
|
|
/* check if VDD is Low Voltage */
|
|
if (!ret) {
|
|
if (regulator_get_value(pwr_reg) < 2700000) {
|
|
writel(SYSCFG_IOCTRLSETR_HSLVEN_TRACE |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_QUADSPI |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_ETH |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_SDMMC |
|
|
SYSCFG_IOCTRLSETR_HSLVEN_SPI,
|
|
syscfg + SYSCFG_IOCTRLSETR);
|
|
|
|
if (!otp)
|
|
pr_err("product_below_2v5=0: HSLVEN protected by HW\n");
|
|
} else {
|
|
if (otp)
|
|
pr_err("product_below_2v5=1: HSLVEN update is destructive, no update as VDD>2.7V\n");
|
|
}
|
|
} else {
|
|
debug("VDD unknown");
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/* activate automatic I/O compensation
|
|
* warning: need to ensure CSI enabled and ready in clock driver
|
|
*/
|
|
writel(SYSCFG_CMPENSETR_MPU_EN, syscfg + SYSCFG_CMPENSETR);
|
|
|
|
while (!(readl(syscfg + SYSCFG_CMPCR) & SYSCFG_CMPCR_READY))
|
|
;
|
|
clrbits_le32(syscfg + SYSCFG_CMPCR, SYSCFG_CMPCR_SW_CTRL);
|
|
#endif
|
|
}
|
|
|
|
/* board dependent setup after realloc */
|
|
int board_init(void)
|
|
{
|
|
/* address of boot parameters */
|
|
gd->bd->bi_boot_params = STM32_DDR_BASE + 0x100;
|
|
|
|
board_key_check();
|
|
|
|
sysconf_init();
|
|
|
|
if (IS_ENABLED(CONFIG_LED))
|
|
led_default_state();
|
|
|
|
return 0;
|
|
}
|
|
|
|
int board_late_init(void)
|
|
{
|
|
#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
|
|
const void *fdt_compat;
|
|
int fdt_compat_len;
|
|
|
|
fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible",
|
|
&fdt_compat_len);
|
|
if (fdt_compat && fdt_compat_len) {
|
|
if (strncmp(fdt_compat, "st,", 3) != 0)
|
|
env_set("board_name", fdt_compat);
|
|
else
|
|
env_set("board_name", fdt_compat + 3);
|
|
}
|
|
#endif
|
|
|
|
/* for DK1/DK2 boards */
|
|
board_check_usb_power();
|
|
|
|
return 0;
|
|
}
|
|
|
|
void board_quiesce_devices(void)
|
|
{
|
|
setup_led(LEDST_OFF);
|
|
}
|