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https://github.com/AsahiLinux/u-boot
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38ef64e6ce
Since commit 34793598c8
("mtd: nand: mxs_nand_spl: Remove the page aligned
access") there are no longer any users of nand_get_mtd. However, it is
still important to know what the page size is so we can allocate a
large-enough buffer. If the image size is not page-aligned, we will go off
the end of the buffer and clobber some memory.
Introduce a new function nand_page_size which returns the page size. For
most drivers it is easy to determine the page size. However, a few need to
be modified since they only keep the page size around temporarily.
It's possible that this patch could cause a regression on some platforms if
the offset is non-aligned and there is invalid address space immediately
before the load address. spl_load_legacy_img does not (except when
compressing) respect bl_len, so only boards with SPL_LOAD_FIT (8 boards) or
SPL_LOAD_IMX_CONTAINER (none in tree) would be affected.
defconfig CONFIG_TEXT_BASE
======================= ================
am335x_evm 0x80800000
am43xx_evm 0x80800000
am43xx_evm_rtconly 0x80800000
am43xx_evm_usbhost_boot 0x80800000
am43xx_hs_evm 0x80800000
dra7xx_evm 0x80800000
gwventana_nand 0x17800000
imx8mn_bsh_smm_s2 0x40200000
All the sitara boards have DDR mapped at 0x80000000. gwventana is an i.MX6Q
which has DDR at 0x10000000. I don't have the IMX8MNRM handy, but on the
i.MX8M DDR starts at 0x40000000. Therefore all of these boards can handle a
little underflow.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
183 lines
3.7 KiB
C
183 lines
3.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* (C) Copyright 2005
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* 2N Telekomunikace, a.s. <www.2n.cz>
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* Ladislav Michl <michl@2n.cz>
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*/
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#include <common.h>
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#include <nand.h>
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#include <errno.h>
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#include <linux/mtd/concat.h>
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#include <linux/mtd/rawnand.h>
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#ifndef CFG_SYS_NAND_BASE_LIST
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#define CFG_SYS_NAND_BASE_LIST { CFG_SYS_NAND_BASE }
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#endif
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int nand_curr_device = -1;
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static struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
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#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
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static struct nand_chip nand_chip[CONFIG_SYS_MAX_NAND_DEVICE];
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static ulong base_address[CONFIG_SYS_MAX_NAND_DEVICE] = CFG_SYS_NAND_BASE_LIST;
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#endif
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static char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
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static unsigned long total_nand_size; /* in kiB */
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struct mtd_info *get_nand_dev_by_index(int dev)
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{
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if (dev < 0 || dev >= CONFIG_SYS_MAX_NAND_DEVICE || !nand_info[dev] ||
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!nand_info[dev]->name)
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return NULL;
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return nand_info[dev];
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}
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int nand_mtd_to_devnum(struct mtd_info *mtd)
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{
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int i;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
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if (mtd && get_nand_dev_by_index(i) == mtd)
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return i;
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}
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return -ENODEV;
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}
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/* Register an initialized NAND mtd device with the U-Boot NAND command. */
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int nand_register(int devnum, struct mtd_info *mtd)
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{
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if (devnum >= CONFIG_SYS_MAX_NAND_DEVICE)
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return -EINVAL;
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nand_info[devnum] = mtd;
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sprintf(dev_name[devnum], "nand%d", devnum);
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mtd->name = dev_name[devnum];
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#ifdef CONFIG_MTD
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/*
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* Add MTD device so that we can reference it later
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* via the mtdcore infrastructure (e.g. ubi).
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*/
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add_mtd_device(mtd);
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#endif
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total_nand_size += mtd->size / 1024;
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if (nand_curr_device == -1)
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nand_curr_device = devnum;
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return 0;
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}
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#if !CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
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static void nand_init_chip(int i)
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{
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struct nand_chip *nand = &nand_chip[i];
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struct mtd_info *mtd = nand_to_mtd(nand);
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ulong base_addr = base_address[i];
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int maxchips = CONFIG_SYS_NAND_MAX_CHIPS;
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if (maxchips < 1)
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maxchips = 1;
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nand->IO_ADDR_R = nand->IO_ADDR_W = (void __iomem *)base_addr;
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if (board_nand_init(nand))
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return;
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if (nand_scan(mtd, maxchips))
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return;
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nand_register(i, mtd);
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}
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#endif
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#ifdef CONFIG_MTD_CONCAT
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static void create_mtd_concat(void)
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{
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struct mtd_info *nand_info_list[CONFIG_SYS_MAX_NAND_DEVICE];
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int nand_devices_found = 0;
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int i;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++) {
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struct mtd_info *mtd = get_nand_dev_by_index(i);
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if (mtd != NULL) {
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nand_info_list[nand_devices_found] = mtd;
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nand_devices_found++;
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}
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}
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if (nand_devices_found > 1) {
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struct mtd_info *mtd;
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char c_mtd_name[16];
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/*
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* We detected multiple devices. Concatenate them together.
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*/
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sprintf(c_mtd_name, "nand%d", nand_devices_found);
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mtd = mtd_concat_create(nand_info_list, nand_devices_found,
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c_mtd_name);
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if (mtd == NULL)
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return;
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nand_register(nand_devices_found, mtd);
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}
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return;
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}
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#else
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static void create_mtd_concat(void)
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{
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}
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#endif
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unsigned long nand_size(void)
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{
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return total_nand_size;
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}
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void nand_init(void)
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{
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static int initialized;
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/*
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* Avoid initializing NAND Flash multiple times,
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* otherwise it will calculate a wrong total size.
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*/
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if (initialized)
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return;
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initialized = 1;
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#if CONFIG_IS_ENABLED(SYS_NAND_SELF_INIT)
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board_nand_init();
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#else
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int i;
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for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
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nand_init_chip(i);
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#endif
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#ifdef CONFIG_SYS_NAND_SELECT_DEVICE
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/*
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* Select the chip in the board/cpu specific driver
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*/
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board_nand_select_device(mtd_to_nand(get_nand_dev_by_index(nand_curr_device)),
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nand_curr_device);
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#endif
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create_mtd_concat();
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}
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unsigned int nand_page_size(void)
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{
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struct mtd_info *mtd = get_nand_dev_by_index(nand_curr_device);
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return mtd ? mtd->writesize : 1;
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}
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