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ee31be429b
The new 32bit DDR controller for TI's am62a family of SoCs shares much of the same functionality with the existing 16bit (am64) and 32bit (j721e) controllers, so this patch reorganizes the existing auto-generated macros for the 16bit and 32bit controllers to make room for the macros for the am62a's controller This patch consists mostly of header/macro renames and additions with a new Kconfig option (K3_AM62A_DDRSS) allowing us to select these new macros during compilation. Signed-off-by: Bryan Brattlof <bb@ti.com>
15 lines
373 B
C
15 lines
373 B
C
/* SPDX-License-Identifier: BSD-3-Clause */
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/*
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* Cadence DDR Driver
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*
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* Copyright (C) 2012-2022 Cadence Design Systems, Inc.
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* Copyright (C) 2018-2022 Texas Instruments Incorporated - https://www.ti.com/
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*/
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#ifndef LPDDR4_AM64_STRUCTS_IF_H
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#define LPDDR4_AM64_STRUCTS_IF_H
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#include <linux/types.h>
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#include "lpddr4_am64_if.h"
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#endif /* LPDDR4_AM64_STRUCTS_IF_H */
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