Leo Yu-Chi Liang 1b2b52f294 riscv: ae350: enable Coherence Manager for ae350 ... If Coherence Manager were not set in the beginning, u-boot-spl would sometimes fail to boot to u-boot proper. Enable CM and I/D cache at the same time in harts_early_init Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>		2021-10-07 16:08:23 +08:00
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ax25	riscv: ae350: enable Coherence Manager for ae350	2021-10-07 16:08:23 +08:00
fu540	board: sifive: use ccache driver instead of helper function	2021-09-07 10:34:29 +08:00
fu740	board: sifive: use ccache driver instead of helper function	2021-09-07 10:34:29 +08:00
generic	riscv: qemu: Switch to use binman to generate u-boot.itb	2021-05-19 17:01:51 +08:00
cpu.c	sysreset: provide SBI based sysreset driver	2021-10-07 16:08:23 +08:00
Makefile	riscv: Move trap handler codes to mtrap.S	2018-12-18 09:56:27 +08:00
mtrap.S	riscv: Add option to print registers on exception	2020-02-10 14:51:08 +08:00
start.S	riscv: cpu: Add callback to init each core	2021-05-05 16:11:22 +08:00
u-boot-spl.lds	riscv: Add _image_binary_end for SPL	2020-06-04 09:44:08 +08:00
u-boot.lds	riscv: Fix breakage caused by linker relaxation	2020-02-10 14:50:53 +08:00