Hou Zhiqiang b392a6d4b0 fsl-layerscape: Add workaround for PCIe erratum A010315 ... As the access to serders protocol unselected PCIe controller will hang. So disable the R/W permission to unselected PCIe controller including its CCSR, IO space and memory space according to the serders protocol field of RCW. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>		2016-09-14 14:07:13 -07:00
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clock.c	driver/ifc: Add 64KB page support	2015-04-23 16:46:50 -07:00
cpu.c	arm: ls102x: add get_svr and IS_SVR_REV helper	2015-12-13 18:27:28 -08:00
fdt.c	arm: ls102xa: Rewrite the logic of ft_fixup_enet_phy_connect_type()	2016-01-28 12:23:22 -06:00
fsl_epu.c	arm: ls102xa: clear EPU registers for deep sleep	2014-12-11 09:35:42 -08:00
fsl_epu.h	arm: ls102xa: clear EPU registers for deep sleep	2014-12-11 09:35:42 -08:00
fsl_ls1_serdes.c	fsl: serdes: ensure accessing the initialized maps of serdes protocol	2016-09-14 14:06:49 -07:00
fsl_ls1_serdes.h	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
ls102xa_sata.c	arm: ls1021a: Adjust sata register default values	2016-01-25 08:24:15 -08:00
ls102xa_serdes.c	arm: ls102xa: Add Freescale LS102xA SoC support	2014-09-08 10:30:32 -07:00
Makefile	arm: ls1021a: merge SoC specific code in a separate file	2015-12-13 18:27:29 -08:00
psci.S	ARMv7: PSCI: ls102xa: add more PSCI v1.0 functions implemention	2016-07-26 09:02:49 -07:00
soc.c	fsl-layerscape: Add workaround for PCIe erratum A010315	2016-09-14 14:07:13 -07:00
spl.c	common: Pass the boot device into spl_boot_mode()	2016-06-26 20:17:22 +02:00
timer.c	arm: ls1021a: Ensure LS1021 ARM Generic Timer CompareValue Set 64-bit	2015-11-30 08:53:01 -08:00