u-boot/arch/arm/dts/cn9130-crb-B.dts
Igal Liberman 341e548eb8 phy: marvell: add support for SFI1
In CP115, comphy4 can be configured into SFI port1
(in addition to SFI0). This patch adds the option
described above.

In addition, rename all existing SFI/XFI references:
COMPHY_TYPE_SFI --> COMPHY_TYPE_SFI0

No functional change for exsiting configuration.

Change-Id: If9176222e0080424ba67347fe4d320215b1ba0c0
Signed-off-by: Igal Liberman <igall@marvell.com>
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
2021-04-29 07:45:24 +02:00

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// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2019 Marvell International Ltd.
*/
#include "cn9130-crb.dtsi"
/ {
model = "CN9130-CRB-B";
compatible = "marvell,cn9130-crb-B",
"marvell,cn9130",
"marvell,armada-ap806-quad",
"marvell,armada-ap806";
};
&cp0_comphy {
phy0 {
phy-type = <COMPHY_TYPE_PEX0>;
};
phy1 {
phy-type = <COMPHY_TYPE_USB3_HOST0>;
};
phy2 {
phy-type = <COMPHY_TYPE_SATA0>;
};
phy3 {
phy-type = <COMPHY_TYPE_USB3_HOST1>;
};
phy4 {
phy-type = <COMPHY_TYPE_SFI0>;
phy-speed = <COMPHY_SPEED_10_3125G>;
};
phy5 {
phy-type = <COMPHY_TYPE_SGMII2>;
phy-speed = <COMPHY_SPEED_3_125G>;
};
};
&cp0_sata0 {
status = "okay";
};
&cp0_pcie0 {
num-lanes = <1>;
/* non-prefetchable memory */
ranges =<0x82000000 0 0xc0000000 0 0xc0000000 0 0x2000000>;
status = "disabled";
};
&cp0_usb3_0 {
status = "okay";
};
&cp0_usb3_1 {
status = "okay";
};