mirror of
https://github.com/AsahiLinux/u-boot
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506df9dc58
1. Convert all linker symbols to char[] type so that we can get the
corresponding address by calling array name 'var' or its address
'&var'. In this way, we can avoid some potential issues[1].
2. Remove unused symbol '_TEXT_BASE'. It has been abandoned and has
not been referenced by any source code.
3. Move '__data_end' to the arch x86's own sections header as it's
only used by x86 arch.
4. Remove some duplicate declared linker symbols. Now we use the
standard header file to declare them.
[1] This patch fixes the boot failure on MIPS target. Error log:
SPL: Image overlaps SPL
Fixes: 1b8a1be1a1 ("spl: spl_legacy: Fix spl_end address")
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
203 lines
4 KiB
C
203 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2016 Freescale Semiconductor, Inc.
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* Copyright 2021 NXP
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*/
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#include <common.h>
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#include <clock_legacy.h>
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#include <fdt_support.h>
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#include <init.h>
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#include <net.h>
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#include <asm/arch/immap_ls102xa.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/fsl_serdes.h>
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#include <asm/arch/ls102xa_stream_id.h>
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#include <asm/global_data.h>
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#include <linux/delay.h>
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#include <asm/arch/ls102xa_devdis.h>
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#include <asm/arch/ls102xa_soc.h>
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#include <asm/sections.h>
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#include <fsl_csu.h>
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#include <fsl_immap.h>
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#include <netdev.h>
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#include <fsl_mdio.h>
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#include <tsec.h>
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#include <spl.h>
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#include <fsl_validate.h>
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#include "../common/sleep.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define DDR_SIZE 0x40000000
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int checkboard(void)
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{
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puts("Board: LS1021AIOT\n");
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#ifndef CONFIG_QSPI_BOOT
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struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR;
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u32 cpldrev;
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cpldrev = in_be32(&dcfg->gpporcr1);
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printf("CPLD: V%d.%d\n", ((cpldrev >> 28) & 0xf), ((cpldrev >> 24) &
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0xf));
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#endif
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return 0;
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}
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void ddrmc_init(void)
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{
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struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR;
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u32 temp_sdram_cfg, tmp;
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG);
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out_be32(&ddr->cs0_bnds, DDR_CS0_BNDS);
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out_be32(&ddr->cs0_config, DDR_CS0_CONFIG);
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out_be32(&ddr->timing_cfg_0, DDR_TIMING_CFG_0);
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out_be32(&ddr->timing_cfg_1, DDR_TIMING_CFG_1);
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out_be32(&ddr->timing_cfg_2, DDR_TIMING_CFG_2);
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out_be32(&ddr->timing_cfg_3, DDR_TIMING_CFG_3);
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out_be32(&ddr->timing_cfg_4, DDR_TIMING_CFG_4);
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out_be32(&ddr->timing_cfg_5, DDR_TIMING_CFG_5);
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out_be32(&ddr->sdram_cfg_2, DDR_SDRAM_CFG_2);
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out_be32(&ddr->ddr_cdr2, DDR_DDR_CDR2);
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out_be32(&ddr->sdram_mode, DDR_SDRAM_MODE);
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out_be32(&ddr->sdram_mode_2, DDR_SDRAM_MODE_2);
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out_be32(&ddr->sdram_interval, DDR_SDRAM_INTERVAL);
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out_be32(&ddr->ddr_wrlvl_cntl, DDR_DDR_WRLVL_CNTL);
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out_be32(&ddr->ddr_wrlvl_cntl_2, DDR_DDR_WRLVL_CNTL_2);
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out_be32(&ddr->ddr_wrlvl_cntl_3, DDR_DDR_WRLVL_CNTL_3);
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out_be32(&ddr->ddr_cdr1, DDR_DDR_CDR1);
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out_be32(&ddr->sdram_clk_cntl, DDR_SDRAM_CLK_CNTL);
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out_be32(&ddr->ddr_zq_cntl, DDR_DDR_ZQ_CNTL);
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out_be32(&ddr->cs0_config_2, DDR_CS0_CONFIG_2);
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/* DDR erratum A-009942 */
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tmp = in_be32(&ddr->debug[28]);
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out_be32(&ddr->debug[28], tmp | 0x0070006f);
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udelay(500);
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temp_sdram_cfg = (DDR_SDRAM_CFG_MEM_EN & ~SDRAM_CFG_BI);
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out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG | temp_sdram_cfg);
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}
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int dram_init(void)
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{
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#if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
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ddrmc_init();
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#endif
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erratum_a008850_post();
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gd->ram_size = DDR_SIZE;
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return 0;
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}
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int board_early_init_f(void)
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{
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struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
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#ifdef CONFIG_TSEC_ENET
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/* clear BD & FR bits for BE BD's and frame data */
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clrbits_be32(&scfg->etsecdmamcr, SCFG_ETSECDMAMCR_LE_BD_FR);
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out_be32(&scfg->etsecmcr, SCFG_ETSECCMCR_GE2_CLK125);
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#endif
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arch_soc_init();
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return 0;
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}
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#ifdef CONFIG_SPL_BUILD
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void board_init_f(ulong dummy)
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{
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/* Clear the BSS */
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memset(__bss_start, 0, __bss_end - __bss_start);
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get_clocks();
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preloader_console_init();
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dram_init();
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/* Allow OCRAM access permission as R/W */
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#ifdef CONFIG_LAYERSCAPE_NS_ACCESS
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enable_layerscape_ns_access();
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#endif
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board_init_r(NULL, 0);
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}
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#endif
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int board_init(void)
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{
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#ifndef CONFIG_SYS_FSL_NO_SERDES
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fsl_serdes_init();
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#endif
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ls102xa_smmu_stream_id_init();
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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return 0;
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}
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#endif
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#if defined(CONFIG_MISC_INIT_R)
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int misc_init_r(void)
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{
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#ifdef CONFIG_FSL_DEVICE_DISABLE
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device_disable(devdis_tbl, ARRAY_SIZE(devdis_tbl));
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#endif
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return 0;
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}
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#endif
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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ft_cpu_setup(blob, bd);
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#ifdef CONFIG_PCI
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ft_pci_setup(blob, bd);
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#endif
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return 0;
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}
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void flash_write16(u16 val, void *addr)
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{
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u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
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__raw_writew(shftval, addr);
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}
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u16 flash_read16(void *addr)
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{
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u16 val = __raw_readw(addr);
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return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
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}
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