mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 09:48:16 +00:00
470 lines
8.8 KiB
ArmAsm
470 lines
8.8 KiB
ArmAsm
/*
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* Lowlevel setup for SMDKV310 board based on S5PC210
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*
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* Copyright (C) 2011 Samsung Electronics
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <version.h>
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#include <asm/arch/cpu.h>
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/*
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* Register usages:
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*
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* r5 has zero always
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* r7 has GPIO part1 base 0x11400000
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* r6 has GPIO part2 base 0x11000000
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*/
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#define MEM_DLLl_ON
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_TEXT_BASE:
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.word CONFIG_SYS_TEXT_BASE
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.globl lowlevel_init
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lowlevel_init:
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push {lr}
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/* r5 has always zero */
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mov r5, #0
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ldr r7, =S5PC210_GPIO_PART1_BASE
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ldr r6, =S5PC210_GPIO_PART2_BASE
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/* check reset status */
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ldr r0, =(S5PC210_POWER_BASE + 0x81C) @ INFORM7
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ldr r1, [r0]
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/* AFTR wakeup reset */
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ldr r2, =S5P_CHECK_DIDLE
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cmp r1, r2
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beq exit_wakeup
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/* Sleep wakeup reset */
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ldr r2, =S5P_CHECK_SLEEP
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cmp r1, r2
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beq wakeup_reset
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/*
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* If U-boot is already running in ram, no need to relocate U-Boot.
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* Memory controller must be configured before relocating U-Boot
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* in ram.
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*/
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ldr r0, =0x00ffffff /* r0 <- Mask Bits*/
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bic r1, pc, r0 /* pc <- current addr of code */
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/* r1 <- unmasked bits of pc */
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ldr r2, _TEXT_BASE /* r2 <- original base addr in ram */
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bic r2, r2, r0 /* r2 <- unmasked bits of r2*/
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cmp r1, r2 /* compare r1, r2 */
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beq 1f /* r0 == r1 then skip sdram init */
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/* init system clock */
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bl system_clock_init
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/* Memory initialize */
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bl mem_ctrl_asm_init
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1:
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/* for UART */
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bl uart_asm_init
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bl tzpc_init
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pop {pc}
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wakeup_reset:
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bl system_clock_init
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bl mem_ctrl_asm_init
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bl tzpc_init
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exit_wakeup:
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/* Load return address and jump to kernel */
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ldr r0, =(S5PC210_POWER_BASE + 0x800) @ INFORM0
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/* r1 = physical address of s5pc210_cpu_resume function */
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ldr r1, [r0]
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/* Jump to kernel*/
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mov pc, r1
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nop
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nop
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/*
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* system_clock_init: Initialize core clock and bus clock.
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* void system_clock_init(void)
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*/
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system_clock_init:
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push {lr}
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ldr r0, =S5PC210_CLOCK_BASE
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/* APLL(1), MPLL(1), CORE(0), HPM(0) */
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ldr r1, =0x0101
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ldr r2, =0x14200 @CLK_SRC_CPU
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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2: subs r1, r1, #1
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bne 2b
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ldr r1, =0x00
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ldr r2, =0x0C210 @CLK_SRC_TOP0
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str r1, [r0, r2]
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ldr r1, =0x00
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ldr r2, =0x0C214 @CLK_SRC_TOP1_OFFSET
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str r1, [r0, r2]
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/* DMC */
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ldr r1, =0x00
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ldr r2, =0x10200 @CLK_SRC_DMC_OFFSET
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str r1, [r0, r2]
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/*CLK_SRC_LEFTBUS */
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ldr r1, =0x00
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ldr r2, =0x04200 @CLK_SRC_LEFTBUS_OFFSET
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str r1, [r0, r2]
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/*CLK_SRC_RIGHTBUS */
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ldr r1, =0x00
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ldr r2, =0x08200 @CLK_SRC_RIGHTBUS_OFFSET
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str r1, [r0, r2]
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/* SATA: SCLKMPLL(0), MMC[0:4]: SCLKMPLL(6) */
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ldr r1, =0x066666
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ldr r2, =0x0C240 @ CLK_SRC_FSYS
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str r1, [r0, r2]
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/* UART[0:4], PWM: SCLKMPLL(6) */
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ldr r1, =0x06666666
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ldr r2, =0x0C250 @CLK_SRC_PERIL0_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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3: subs r1, r1, #1
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bne 3b
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/*
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* CLK_DIV_CPU0:
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*
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* PCLK_DBG_RATIO[20] 0x1
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* ATB_RATIO[16] 0x3
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* PERIPH_RATIO[12] 0x3
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* COREM1_RATIO[8] 0x7
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* COREM0_RATIO[4] 0x3
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*/
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ldr r1, =0x0133730
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ldr r2, =0x14500 @CLK_DIV_CPU0_OFFSET
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str r1, [r0, r2]
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/* CLK_DIV_CPU1: COPY_RATIO [0] 0x3 */
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ldr r1, =0x03
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ldr r2, =0x14504 @CLK_DIV_CPU1_OFFSET
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str r1, [r0, r2]
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/*
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* CLK_DIV_DMC0:
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*
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* CORE_TIMERS_RATIO[28] 0x1
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* COPY2_RATIO[24] 0x3
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* DMCP_RATIO[20] 0x1
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* DMCD_RATIO[16] 0x1
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* DMC_RATIO[12] 0x1
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* DPHY_RATIO[8] 0x1
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* ACP_PCLK_RATIO[4] 0x1
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* ACP_RATIO[0] 0x3
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*/
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ldr r1, =0x13111113
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ldr r2, =0x010500 @CLK_DIV_DMC0_OFFSET
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str r1, [r0, r2]
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/*
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* CLK_DIV_DMC1:
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*
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* DPM_RATIO[24] 0x1
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* DVSEM_RATIO[16] 0x1
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* PWI_RATIO[8] 0x1
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*/
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ldr r1, =0x01010100
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ldr r2, =0x010504 @CLK_DIV_DMC1_OFFSET
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str r1, [r0, r2]
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/*
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* CLK_DIV_LEFRBUS:
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*
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* GPL_RATIO[4] 0x1
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* GDL_RATIO[0] 0x3
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*/
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ldr r1, =0x013
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ldr r2, =0x04500 @CLK_DIV_LEFTBUS_OFFSET
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str r1, [r0, r2]
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/*
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* CLK_DIV_RIGHTBUS:
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*
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* GPR_RATIO[4] 0x1
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* GDR_RATIO[0] 0x3
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*/
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ldr r1, =0x013
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ldr r2, =0x08500 @CLK_DIV_RIGHTBUS_OFFSET
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str r1, [r0, r2]
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/*
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* CLK_DIV_TOP:
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*
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* ONENAND_RATIO[16] 0x0
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* ACLK_133_RATIO[12] 0x5
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* ACLK_160_RATIO[8] 0x4
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* ACLK_100_RATIO[4] 0x7
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* ACLK_200_RATIO[0] 0x3
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*/
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ldr r1, =0x05473
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ldr r2, =0x0C510 @CLK_DIV_TOP_OFFSET
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str r1, [r0, r2]
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/* MMC[0:1] */
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ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
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ldr r2, =0x0C544 @ CLK_DIV_FSYS1
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str r1, [r0, r2]
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/* MMC[2:3] */
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ldr r1, =0x000f000f /* 800(MPLL) / (15 + 1) */
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ldr r2, =0x0C548 @ CLK_DIV_FSYS2
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str r1, [r0, r2]
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/* MMC4 */
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ldr r1, =0x000f /* 800(MPLL) / (15 + 1) */
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ldr r2, =0x0C54C @ CLK_DIV_FSYS3
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x10000
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4: subs r1, r1, #1
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bne 4b
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/*
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* CLK_DIV_PERIL0:
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*
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* UART5_RATIO[20] 8
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* UART4_RATIO[16] 8
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* UART3_RATIO[12] 8
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* UART2_RATIO[8] 8
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* UART1_RATIO[4] 8
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* UART0_RATIO[0] 8
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*/
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ldr r1, =0x774777
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ldr r2, =0x0C550 @CLK_DIV_PERIL0_OFFSET
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str r1, [r0, r2]
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/* SLIMBUS: ???, PWM */
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ldr r1, =0x8
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ldr r2, =0x0C55C @ CLK_DIV_PERIL3
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str r1, [r0, r2]
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/* Set PLL locktime */
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ldr r1, =0x01C20
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ldr r2, =0x014000 @APLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =0x01C20
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ldr r2, =0x014008 @MPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =0x01C20
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ldr r2, =0x0C010 @EPLL_LOCK_OFFSET
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str r1, [r0, r2]
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ldr r1, =0x01C20
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ldr r2, =0x0C020 @VPLL_LOCK_OFFSET
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str r1, [r0, r2]
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/*
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* APLL_CON1:
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*
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* APLL_AFC_ENB[31] 0x1
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* APLL_AFC[0] 0xC
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*/
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ldr r1, =0x8000000C
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ldr r2, =0x014104 @APLL_CON1_OFFSET
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str r1, [r0, r2]
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/*
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* APLL_CON0:
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*
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* APLL_MDIV[16] 0xFA
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* APLL_PDIV[8] 0x6
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* APLL_SDIV[0] 0x1
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*/
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ldr r1, =0x80FA0601
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ldr r2, =0x014100 @APLL_CON0_OFFSET
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str r1, [r0, r2]
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/*
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* MPLL_CON1:
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*
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* MPLL_AFC_ENB[31] 0x1
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* MPLL_AFC[0] 0x1C
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*/
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ldr r1, =0x0000001C
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ldr r2, =0x01410C @MPLL_CON1_OFFSET
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str r1, [r0, r2]
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/*
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* MPLL_CON0:
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*
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* MPLL_MDIV[16] 0xC8
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* MPLL_PDIV[8] 0x6
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* MPLL_SDIV[0] 0x1
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*/
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ldr r1, =0x80C80601
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ldr r2, =0x014108 @MPLL_CON0_OFFSET
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str r1, [r0, r2]
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/* EPLL */
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ldr r1, =0x0
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ldr r2, =0x0C114 @EPLL_CON1_OFFSET
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str r1, [r0, r2]
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/*
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* EPLL_CON0:
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*
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* EPLL_MDIV[16] 0x30
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* EPLL_PDIV[8] 0x3
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* EPLL_SDIV[0] 0x2
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*/
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ldr r1, =0x80300302
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ldr r2, =0x0C110 @EPLL_CON0_OFFSET
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str r1, [r0, r2]
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/*
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* VPLL_CON1:
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*
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* VPLL_MRR[24] 0x11
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* VPLL_MFR[16] 0x0
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* VPLL_K[0] 0x400
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*/
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ldr r1, =0x11000400
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ldr r2, =0x0C124 @VPLL_CON1_OFFSET
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str r1, [r0, r2]
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/*
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* VPLL_CON0:
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*
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* VPLL_MDIV[16] 0x35
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* VPLL_PDIV[8] 0x3
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* VPLL_SDIV[0] 0x2
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*/
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ldr r1, =0x80350302
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ldr r2, =0x0C120 @VPLL_CON0_OFFSET
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str r1, [r0, r2]
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/* wait ?us */
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mov r1, #0x30000
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3: subs r1, r1, #1
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bne 3b
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pop {pc}
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/*
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* uart_asm_init: Initialize UART in asm mode, 115200bps fixed.
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* void uart_asm_init(void)
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*/
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.globl uart_asm_init
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uart_asm_init:
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/* setup UART0-UART3 GPIOs (part1) */
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mov r0, r7
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ldr r1, =0x22222222
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str r1, [r0, #0x00] @ S5PC210_GPIO_A0_OFFSET
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ldr r1, =0x00222222
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str r1, [r0, #0x20] @ S5PC210_GPIO_A1_OFFSET
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ldr r0, =S5PC210_UART_BASE
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add r0, r0, #S5PC210_DEFAULT_UART_OFFSET
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ldr r1, =0x3C5
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str r1, [r0, #0x4]
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ldr r1, =0x111
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str r1, [r0, #0x8]
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ldr r1, =0x3
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str r1, [r0, #0x0]
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ldr r1, =0x35
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str r1, [r0, #0x28]
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ldr r1, =0x4
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str r1, [r0, #0x2c]
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mov pc, lr
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nop
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nop
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nop
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/* Setting TZPC[TrustZone Protection Controller] */
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tzpc_init:
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ldr r0, =0x10110000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10120000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10130000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10140000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10150000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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ldr r0, =0x10160000
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mov r1, #0x0
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str r1, [r0]
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mov r1, #0xff
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str r1, [r0, #0x0804]
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str r1, [r0, #0x0810]
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str r1, [r0, #0x081C]
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str r1, [r0, #0x0828]
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mov pc, lr
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