Shengzhou Liu 02fb276157 fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum ... - add additional function erratum_a009942_check_cpo to check if the board needs tuning CPO calibration for optimal setting. - move ERRATUM_A009942(with revision to check cpo_sample option) from fsl_ddr_gen4.c to ctrl_regs.c for reuse on all DDR4/DDR3 parts. - move ERRATUM_A008378 from fsl_ddr_gen4.c to ctrl_regs.c - remove obsolete ERRATUM_A004934 which is replaced with ERRATUM_A009942. Signed-off-by: Shengzhou Liu <Shengzhou.Liu@nxp.com> [YS: Replaced CONFIG_QEMU_E500 with CONFIG_ARCH_QEMU_E500] Reviewed-by: York Sun <york.sun@nxp.com>		2016-12-05 08:31:45 -08:00
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altera	ddr: altera: Configuring SDRAM extra cycles timing parameters	2016-10-27 08:03:07 +02:00
fsl	fsl/ddr: Add erratum_a009942_check_cpo and clean related erratum	2016-12-05 08:31:45 -08:00
marvell	Various, accumulated typos collected from around the tree.	2016-10-06 20:57:40 -04:00
microchip	drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.	2016-02-01 22:14:01 +01:00