mirror of
https://github.com/AsahiLinux/u-boot
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b564aa2740
Add sdhci node to SPL and u-boot,spl-boot-order. Also add more supported mmc modes and pinctrl. Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
80 lines
1.1 KiB
Text
80 lines
1.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
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*/
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#include "rockchip-u-boot.dtsi"
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/ {
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dmc {
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compatible = "rockchip,rk3588-dmc";
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bootph-all;
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status = "okay";
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};
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pmu1_grf: syscon@fd58a000 {
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bootph-all;
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compatible = "rockchip,rk3588-pmu1-grf", "syscon";
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reg = <0x0 0xfd58a000 0x0 0x2000>;
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};
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otp: nvmem@fecc0000 {
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compatible = "rockchip,rk3588-otp";
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reg = <0x0 0xfecc0000 0x0 0x400>;
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#address-cells = <1>;
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#size-cells = <1>;
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status = "okay";
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cpu_id: id@7 {
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reg = <0x07 0x10>;
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};
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};
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rng: rng@fe378000 {
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compatible = "rockchip,trngv1";
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reg = <0x0 0xfe378000 0x0 0x200>;
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status = "disabled";
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};
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};
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&xin24m {
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bootph-all;
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status = "okay";
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};
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&cru {
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bootph-pre-ram;
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status = "okay";
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};
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&sys_grf {
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bootph-pre-ram;
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status = "okay";
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};
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&scmi {
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bootph-pre-ram;
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};
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&scmi_clk {
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bootph-pre-ram;
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};
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&sdmmc {
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bootph-pre-ram;
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u-boot,spl-fifo-mode;
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};
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&sdhci {
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bootph-pre-ram;
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};
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&uart2 {
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clock-frequency = <24000000>;
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bootph-pre-ram;
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status = "okay";
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};
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&ioc {
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bootph-pre-ram;
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};
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