mirror of
https://github.com/AsahiLinux/u-boot
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35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
146 lines
2.8 KiB
C
146 lines
2.8 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright 2019 Toradex
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/imx8-pins.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/sci/sci.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/gpio.h>
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#include <asm/io.h>
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#include <env.h>
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#include <errno.h>
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#include <linux/libfdt.h>
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#include "../common/tdx-cfg-block.h"
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL ((SC_PAD_CONFIG_OUT_IN << PADRING_CONFIG_SHIFT) | \
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(SC_PAD_ISO_OFF << PADRING_LPCONFIG_SHIFT) | \
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(SC_PAD_28FDSOI_DSE_DV_HIGH << PADRING_DSE_SHIFT) | \
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(SC_PAD_28FDSOI_PS_PU << PADRING_PULL_SHIFT))
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static iomux_cfg_t uart1_pads[] = {
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SC_P_UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
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SC_P_UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
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};
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static void setup_iomux_uart(void)
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{
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imx8_iomux_setup_multiple_pads(uart1_pads, ARRAY_SIZE(uart1_pads));
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}
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void board_mem_get_layout(u64 *phys_sdram_1_start,
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u64 *phys_sdram_1_size,
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u64 *phys_sdram_2_start,
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u64 *phys_sdram_2_size)
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{
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u32 is_quadplus = 0, val = 0;
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sc_err_t scierr = sc_misc_otp_fuse_read(-1, 6, &val);
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if (scierr == SC_ERR_NONE) {
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/* QP has one A72 core disabled */
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is_quadplus = ((val >> 4) & 0x3) != 0x0;
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}
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*phys_sdram_1_start = PHYS_SDRAM_1;
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*phys_sdram_1_size = PHYS_SDRAM_1_SIZE;
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*phys_sdram_2_start = PHYS_SDRAM_2;
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if (is_quadplus)
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/* Our QP based SKUs only have 2 GB RAM (PHYS_SDRAM_1_SIZE) */
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*phys_sdram_2_size = 0x0UL;
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else
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*phys_sdram_2_size = PHYS_SDRAM_2_SIZE;
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}
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int board_early_init_f(void)
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{
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sc_pm_clock_rate_t rate = SC_80MHZ;
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sc_err_t err = 0;
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/* Set UART1 clock root to 80 MHz and enable it */
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err = sc_pm_setup_uart(SC_R_UART_1, rate);
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if (err != SC_ERR_NONE)
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return 0;
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setup_iomux_uart();
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return 0;
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}
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#if CONFIG_IS_ENABLED(DM_GPIO)
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static void board_gpio_init(void)
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{
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/* TODO */
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}
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#else
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static inline void board_gpio_init(void) {}
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#endif
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#if IS_ENABLED(CONFIG_FEC_MXC)
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#include <miiphy.h>
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int board_phy_config(struct phy_device *phydev)
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{
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if (phydev->drv->config)
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phydev->drv->config(phydev);
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return 0;
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}
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#endif
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int checkboard(void)
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{
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puts("Model: Toradex Apalis iMX8\n");
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build_info();
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print_bootinfo();
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return 0;
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}
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int board_init(void)
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{
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board_gpio_init();
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return 0;
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}
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/*
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* Board specific reset that is system reset.
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*/
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void reset_cpu(void)
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{
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/* TODO */
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}
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#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
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int ft_board_setup(void *blob, struct bd_info *bd)
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{
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return ft_common_board_setup(blob, bd);
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}
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#endif
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int board_mmc_get_env_dev(int devno)
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{
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return devno;
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}
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int board_late_init(void)
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{
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#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
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/* TODO move to common */
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env_set("board_name", "Apalis iMX8QM");
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env_set("board_rev", "v1.0");
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#endif
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return 0;
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}
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