mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-23 03:23:47 +00:00
35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
458 lines
14 KiB
C
458 lines
14 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2016 Nelson Integration, LLC
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* Author: Eric Nelson <eric@nelint.com>
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*/
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#include <common.h>
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#include <cpu_func.h>
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#include <init.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/arch/iomux.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/crm_regs.h>
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#include <asm/arch/mx6-ddr.h>
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#include <asm/arch/mx6-pins.h>
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#include <asm/arch/sys_proto.h>
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#include <spl.h>
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DECLARE_GLOBAL_DATA_PTR;
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#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \
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PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \
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PAD_CTL_SRE_FAST | PAD_CTL_HYS)
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static iomux_v3_cfg_t const uart_pads[] = {
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#ifdef CONFIG_UART2_EIM_D26_27
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IOMUX_PADS(PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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#elif defined(CONFIG_UART1_CSI0_DAT10_11)
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IOMUX_PADS(PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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#elif defined(CONFIG_UART1_SD3_DAT6_7)
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IOMUX_PADS(PAD_SD3_DAT6__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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IOMUX_PADS(PAD_SD3_DAT7__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL)),
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#elif defined(CONFIG_UART1_UART1)
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MX6_PAD_UART1_TXD__UART1_TXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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MX6_PAD_UART1_RXD__UART1_RXD | MUX_PAD_CTRL(UART_PAD_CTRL),
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#else
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#error select UART console pads
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#endif
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};
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#ifdef CONFIG_DDR3
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#define GRP_DDRTYPE 0x000C0000
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#else
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#define GRP_DDRTYPE 0x00080000
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#endif
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/* all existing designs have this disabled */
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#define DDR_PKE 0
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/* use Kconfig for ODT and DRIVE_STRENGTH */
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#define DDR_ODT \
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(CONFIG_DDR_ODT << 8)
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#define DRAM_DRIVE_STRENGTH \
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(CONFIG_DRAM_DRIVE_STRENGTH << 3)
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/* configure MX6Q/DUAL mmdc DDR io registers */
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static struct mx6dq_iomux_ddr_regs const mx6dq_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
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.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs4 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs5 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs6 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs7 = DRAM_DRIVE_STRENGTH,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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};
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/* configure MX6Q/DUAL mmdc GRP io registers */
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static struct mx6dq_iomux_grp_regs const mx6dq_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = GRP_DDRTYPE,
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.grp_ddrmode_ctl = DDR_ODT,
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/* disable DDR pullups */
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.grp_ddrpke = DDR_PKE,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = DRAM_DRIVE_STRENGTH,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = DRAM_DRIVE_STRENGTH,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = DDR_ODT,
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.grp_b0ds = DRAM_DRIVE_STRENGTH,
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.grp_b1ds = DRAM_DRIVE_STRENGTH,
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.grp_b2ds = DRAM_DRIVE_STRENGTH,
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.grp_b3ds = DRAM_DRIVE_STRENGTH,
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.grp_b4ds = DRAM_DRIVE_STRENGTH,
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.grp_b5ds = DRAM_DRIVE_STRENGTH,
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.grp_b6ds = DRAM_DRIVE_STRENGTH,
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.grp_b7ds = DRAM_DRIVE_STRENGTH,
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};
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static struct mx6sdl_iomux_ddr_regs const mx6sdl_ddr_ioregs = {
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/* SDCLK[0:1], CAS, RAS, Reset: Differential input, 40ohm */
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.dram_sdclk_0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_sdclk_1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_cas = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_ras = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_reset = DDR_ODT + DRAM_DRIVE_STRENGTH,
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/* SDCKE[0:1]: 100k pull-up */
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.dram_sdcke0 = 0x00003000,
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.dram_sdcke1 = 0x00003000,
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/* SDBA2: pull-up disabled */
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.dram_sdba2 = 0x00000000,
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/* SDODT[0:1]: 100k pull-up, 40 ohm */
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.dram_sdodt0 = 0x00003000 + DRAM_DRIVE_STRENGTH,
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.dram_sdodt1 = 0x00003000 + DRAM_DRIVE_STRENGTH,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs4 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs5 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs6 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs7 = DRAM_DRIVE_STRENGTH,
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/* DQM[0:7]: Differential input, 40 ohm */
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.dram_dqm0 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm1 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm2 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm3 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm4 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm5 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm6 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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.dram_dqm7 = DDR_ODT + DRAM_DRIVE_STRENGTH,
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};
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/* configure MX6SOLO/DUALLITE mmdc GRP io registers */
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static struct mx6sdl_iomux_grp_regs const mx6sdl_grp_ioregs = {
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/* DDR3 */
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.grp_ddr_type = GRP_DDRTYPE,
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/* SDQS[0:7]: Differential input, 40 ohm */
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.grp_ddrmode_ctl = DDR_ODT,
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/* disable DDR pullups */
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.grp_ddrpke = DDR_PKE,
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/* ADDR[00:16], SDBA[0:1]: 40 ohm */
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.grp_addds = DRAM_DRIVE_STRENGTH,
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/* CS0/CS1/SDBA2/CKE0/CKE1/SDWE: 40 ohm */
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.grp_ctlds = DRAM_DRIVE_STRENGTH,
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/* DATA[00:63]: Differential input, 40 ohm */
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.grp_ddrmode = DDR_ODT,
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.grp_b0ds = DRAM_DRIVE_STRENGTH,
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.grp_b1ds = DRAM_DRIVE_STRENGTH,
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.grp_b2ds = DRAM_DRIVE_STRENGTH,
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.grp_b3ds = DRAM_DRIVE_STRENGTH,
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.grp_b4ds = DRAM_DRIVE_STRENGTH,
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.grp_b5ds = DRAM_DRIVE_STRENGTH,
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.grp_b6ds = DRAM_DRIVE_STRENGTH,
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.grp_b7ds = DRAM_DRIVE_STRENGTH,
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};
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const struct mx6sl_iomux_ddr_regs mx6sl_ddr_ioregs = {
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.dram_sdqs0 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs1 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs2 = DRAM_DRIVE_STRENGTH,
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.dram_sdqs3 = DRAM_DRIVE_STRENGTH,
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.dram_dqm0 = DRAM_DRIVE_STRENGTH,
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.dram_dqm1 = DRAM_DRIVE_STRENGTH,
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.dram_dqm2 = DRAM_DRIVE_STRENGTH,
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.dram_dqm3 = DRAM_DRIVE_STRENGTH,
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.dram_cas = DRAM_DRIVE_STRENGTH,
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.dram_ras = DRAM_DRIVE_STRENGTH,
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.dram_sdclk_0 = DRAM_DRIVE_STRENGTH,
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.dram_reset = DRAM_DRIVE_STRENGTH,
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.dram_sdba2 = 0x00020000,
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.dram_odt0 = 0x00030000 + DRAM_DRIVE_STRENGTH,
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.dram_odt1 = 0x00030000 + DRAM_DRIVE_STRENGTH,
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};
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const struct mx6sl_iomux_grp_regs mx6sl_grp_ioregs = {
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.grp_b0ds = DRAM_DRIVE_STRENGTH,
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.grp_b1ds = DRAM_DRIVE_STRENGTH,
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.grp_b2ds = DRAM_DRIVE_STRENGTH,
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.grp_b3ds = DRAM_DRIVE_STRENGTH,
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.grp_addds = DRAM_DRIVE_STRENGTH,
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.grp_ctlds = DRAM_DRIVE_STRENGTH,
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.grp_ddrmode_ctl = DDR_ODT,
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.grp_ddrpke = DDR_PKE,
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.grp_ddrmode = DDR_ODT,
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.grp_ddr_type = GRP_DDRTYPE,
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};
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static struct mx6_ddr_sysinfo const sysinfo = {
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/* width of data bus:0=16,1=32,2=64 */
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#if CONFIG_DDRWIDTH == 32
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.dsize = 1,
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#elif CONFIG_DDRWIDTH == 64
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.dsize = 2,
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#else
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#error missing CONFIG_DDRWIDTH
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#endif
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/* config for full 4GB range so that get_mem_size() works */
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.cs_density = 32, /* 32Gb per CS */
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/* # of chip selects */
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.ncs = CONFIG_DDRCS,
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.cs1_mirror = 0,
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.bi_on = 1, /* Bank interleaving enabled */
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.rtt_nom = CONFIG_RTT_NOM,
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.rtt_wr = CONFIG_RTT_WR,
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.ralat = CONFIG_RALAT, /* Read additional latency */
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.walat = CONFIG_WALAT, /* Write additional latency */
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.mif3_mode = 3, /* Command prediction working mode */
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#ifdef CONFIG_DDR3
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.rst_to_cke = 0x23, /* 33 cycles, 500us (JEDEC default) */
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.sde_to_rst = 0x10, /* JEDEC value for LPDDR2 - 200us */
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.pd_fast_exit = 0, /* immaterial for calibration */
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.ddr_type = DDR_TYPE_DDR3,
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#else
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.rst_to_cke = 0x10, /* JEDEC value for LPDDR2: 200us */
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.sde_to_rst = 0, /* LPDDR2 does not need this field */
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.pd_fast_exit = 0, /* immaterial for calibration */
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.ddr_type = DDR_TYPE_LPDDR2,
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#endif
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.refsel = CONFIG_REFSEL,
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.refr = CONFIG_REFR,
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};
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#ifdef CONFIG_MT41K512M16TNA
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/* Micron MT41K512M16TNA-125 */
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static struct mx6_ddr3_cfg const ddrtype = {
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.mem_speed = 1600,
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.density = 8,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 1,
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.trcd = 1375,
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.trcmin = 5062,
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.trasmin = 3750,
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};
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#elif defined(CONFIG_MT41K128M16JT)
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/* Micron MT41K128M16JT-125 */
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static struct mx6_ddr3_cfg const ddrtype = {
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.mem_speed = 1600,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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#elif defined(CONFIG_H5TQ4G63AFR)
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/* Hynix H5TQ4G63AFR */
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static struct mx6_ddr3_cfg const ddrtype = {
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.mem_speed = 1600,
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.density = 4,
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.width = 16,
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.banks = 8,
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.rowaddr = 15,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1375,
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.trcmin = 4875,
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.trasmin = 3500,
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};
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#elif defined CONFIG_H5TQ2G63DFR
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/* Hynix H5TQ2G63DFR */
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static struct mx6_ddr3_cfg const ddrtype = {
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.mem_speed = 1333,
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.density = 2,
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.width = 16,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.pagesz = 2,
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.trcd = 1350,
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.trcmin = 4950,
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.trasmin = 3600,
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};
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#elif defined(CONFIG_MT42L256M32D2LG)
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/* Micron MT42L256M32D2LG */
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static struct mx6_lpddr2_cfg ddrtype = {
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.mem_speed = 800,
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.density = 4,
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.width = 32,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.trcd_lp = 2000,
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.trppb_lp = 2000,
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.trpab_lp = 2250,
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.trasmin = 4200,
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};
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#elif defined(CONFIG_MT29PZZZ4D4BKESK)
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/* Micron MT29PZZZ4D4BKESK */
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static struct mx6_lpddr2_cfg ddrtype = {
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.mem_speed = 800,
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.density = 4,
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.width = 32,
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.banks = 8,
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.rowaddr = 14,
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.coladdr = 10,
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.trcd_lp = 2000,
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.trppb_lp = 2000,
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.trpab_lp = 2250,
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.trasmin = 4200,
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};
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#else
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#error please select DDR type using menuconfig
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#endif
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static void ccgr_init(void)
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{
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struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
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/* FIXME: these should probably be checked, especially
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* for i.MX6SL, UL, ULL
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*/
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writel(0x00C03F3F, &ccm->CCGR0);
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writel(0x0030FC03, &ccm->CCGR1);
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writel(0x0FFFC000, &ccm->CCGR2);
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writel(0x3FF00000, &ccm->CCGR3);
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writel(0x00FFF300, &ccm->CCGR4);
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writel(0x0F0000C3, &ccm->CCGR5);
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writel(0x000003FF, &ccm->CCGR6);
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}
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static void display_calibration(struct mx6_mmdc_calibration *calib)
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{
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printf(".p0_mpdgctrl0\t= 0x%08X\n", calib->p0_mpdgctrl0);
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printf(".p0_mpdgctrl1\t= 0x%08X\n", calib->p0_mpdgctrl1);
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printf(".p0_mprddlctl\t= 0x%08X\n", calib->p0_mprddlctl);
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printf(".p0_mpwrdlctl\t= 0x%08X\n", calib->p0_mpwrdlctl);
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printf(".p0_mpwldectrl0\t= 0x%08X\n", calib->p0_mpwldectrl0);
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printf(".p0_mpwldectrl1\t= 0x%08X\n", calib->p0_mpwldectrl1);
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if (sysinfo.dsize == 2) {
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printf(".p1_mpdgctrl0\t= 0x%08X\n", calib->p1_mpdgctrl0);
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printf(".p1_mpdgctrl1\t= 0x%08X\n", calib->p1_mpdgctrl1);
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printf(".p1_mprddlctl\t= 0x%08X\n", calib->p1_mprddlctl);
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printf(".p1_mpwrdlctl\t= 0x%08X\n", calib->p1_mpwrdlctl);
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printf(".p1_mpwldectrl0\t= 0x%08X\n", calib->p1_mpwldectrl0);
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printf(".p1_mpwldectrl1\t= 0x%08X\n", calib->p1_mpwldectrl1);
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}
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#ifdef CONFIG_IMXIMAGE_OUTPUT
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printf("DATA 4 MX6_MMDC_P0_MPDGCTRL0\t= 0x%08X\n", calib->p0_mpdgctrl0);
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printf("DATA 4 MX6_MMDC_P0_MPDGCTRL1\t= 0x%08X\n", calib->p0_mpdgctrl1);
|
|
printf("DATA 4 MX6_MMDC_P0_MPRDDLCTL\t= 0x%08X\n", calib->p0_mprddlctl);
|
|
printf("DATA 4 MX6_MMDC_P0_MPWRDLCTL\t= 0x%08X\n", calib->p0_mpwrdlctl);
|
|
printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL0\t= 0x%08X\n",
|
|
calib->p0_mpwldectrl0);
|
|
printf("DATA 4 MX6_MMDC_P0_MPWLDECTRL1\t= 0x%08X\n",
|
|
calib->p0_mpwldectrl1);
|
|
if (sysinfo.dsize == 2) {
|
|
printf("DATA 4 MX6_MMDC_P1_MPDGCTRL0\t= 0x%08X\n",
|
|
calib->p1_mpdgctrl0);
|
|
printf("DATA 4 MX6_MMDC_P1_MPDGCTRL1\t= 0x%08X\n",
|
|
calib->p1_mpdgctrl1);
|
|
printf("DATA 4 MX6_MMDC_P1_MPRDDLCTL\t= 0x%08X\n",
|
|
calib->p1_mprddlctl);
|
|
printf("DATA 4 MX6_MMDC_P1_MPWRDLCTL\t= 0x%08X\n",
|
|
calib->p1_mpwrdlctl);
|
|
printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL0\t= 0x%08X\n",
|
|
calib->p1_mpwldectrl0);
|
|
printf("DATA 4 MX6_MMDC_P1_MPWLDECTRL1\t= 0x%08X\n",
|
|
calib->p1_mpwldectrl1);
|
|
}
|
|
#endif
|
|
}
|
|
|
|
/*
|
|
* called from C runtime startup code (arch/arm/lib/crt0.S:_main)
|
|
* - we have a stack and a place to store GD, both in SRAM
|
|
* - no variable global data is available
|
|
*/
|
|
void board_init_f(ulong dummy)
|
|
{
|
|
int errs;
|
|
struct mx6_mmdc_calibration calibration = {0};
|
|
|
|
memset((void *)gd, 0, sizeof(struct global_data));
|
|
|
|
/* write leveling calibration defaults */
|
|
calibration.p0_mpwrdlctl = 0x40404040;
|
|
calibration.p1_mpwrdlctl = 0x40404040;
|
|
|
|
/* setup AIPS and disable watchdog */
|
|
arch_cpu_init();
|
|
|
|
ccgr_init();
|
|
|
|
SETUP_IOMUX_PADS(uart_pads);
|
|
|
|
/* setup GP timer */
|
|
timer_init();
|
|
|
|
/* UART clocks enabled and gd valid - init serial console */
|
|
preloader_console_init();
|
|
|
|
if (sysinfo.dsize != 1) {
|
|
if (is_cpu_type(MXC_CPU_MX6SX) ||
|
|
is_cpu_type(MXC_CPU_MX6UL) ||
|
|
is_cpu_type(MXC_CPU_MX6ULL) ||
|
|
is_cpu_type(MXC_CPU_MX6SL)) {
|
|
printf("cpu type 0x%x doesn't support 64-bit bus\n",
|
|
get_cpu_type());
|
|
reset_cpu();
|
|
}
|
|
}
|
|
#ifdef CONFIG_MX6SL
|
|
mx6sl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sl_ddr_ioregs,
|
|
&mx6sl_grp_ioregs);
|
|
#else
|
|
if (is_cpu_type(MXC_CPU_MX6Q)) {
|
|
mx6dq_dram_iocfg(CONFIG_DDRWIDTH, &mx6dq_ddr_ioregs,
|
|
&mx6dq_grp_ioregs);
|
|
} else {
|
|
mx6sdl_dram_iocfg(CONFIG_DDRWIDTH, &mx6sdl_ddr_ioregs,
|
|
&mx6sdl_grp_ioregs);
|
|
}
|
|
#endif
|
|
mx6_dram_cfg(&sysinfo, &calibration, &ddrtype);
|
|
|
|
errs = mmdc_do_write_level_calibration(&sysinfo);
|
|
if (errs) {
|
|
printf("error %d from write level calibration\n", errs);
|
|
} else {
|
|
errs = mmdc_do_dqs_calibration(&sysinfo);
|
|
if (errs) {
|
|
printf("error %d from dqs calibration\n", errs);
|
|
} else {
|
|
printf("completed successfully\n");
|
|
mmdc_read_calibration(&sysinfo, &calibration);
|
|
display_calibration(&calibration);
|
|
}
|
|
}
|
|
}
|