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The PCH (Platform Controller Hub) includes an LPC (Low Pin Count) device which provides a serial port. This is accessible on Chromebooks, so enable it early in the boot process. Signed-off-by: Simon Glass <sjg@chromium.org>
48 lines
1.6 KiB
C
48 lines
1.6 KiB
C
/*
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* Copyright (c) 2014 Google, Inc
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*
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* From Coreboot src/southbridge/intel/bd82x6x/pch.h
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*
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* Copyright (C) 2008-2009 coresystems GmbH
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* Copyright (C) 2012 The Chromium OS Authors. All rights reserved.
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*
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* SPDX-License-Identifier: GPL-2.0
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*/
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#ifndef _ASM_ARCH_PCH_H
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#define _ASM_ARCH_PCH_H
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#include <pci.h>
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/* PCI Configuration Space (D31:F0): LPC */
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#define PCH_LPC_DEV PCI_BDF(0, 0x1f, 0)
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#define LPC_IO_DEC 0x80 /* IO Decode Ranges Register */
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#define LPC_EN 0x82 /* LPC IF Enables Register */
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#define CNF2_LPC_EN (1 << 13) /* 0x4e/0x4f */
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#define CNF1_LPC_EN (1 << 12) /* 0x2e/0x2f */
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#define MC_LPC_EN (1 << 11) /* 0x62/0x66 */
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#define KBC_LPC_EN (1 << 10) /* 0x60/0x64 */
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#define GAMEH_LPC_EN (1 << 9) /* 0x208/0x20f */
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#define GAMEL_LPC_EN (1 << 8) /* 0x200/0x207 */
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#define FDD_LPC_EN (1 << 3) /* LPC_IO_DEC[12] */
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#define LPT_LPC_EN (1 << 2) /* LPC_IO_DEC[9:8] */
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#define COMB_LPC_EN (1 << 1) /* LPC_IO_DEC[6:4] */
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#define COMA_LPC_EN (1 << 0) /* LPC_IO_DEC[3:2] */
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#define LPC_GEN1_DEC 0x84 /* LPC IF Generic Decode Range 1 */
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#define LPC_GEN2_DEC 0x88 /* LPC IF Generic Decode Range 2 */
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#define LPC_GEN3_DEC 0x8c /* LPC IF Generic Decode Range 3 */
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#define LPC_GEN4_DEC 0x90 /* LPC IF Generic Decode Range 4 */
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#define LPC_GENX_DEC(x) (0x84 + 4 * (x))
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/**
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* lpc_early_init() - set up LPC serial ports and other early things
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*
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* @blob: Device tree blob
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* @node: Offset of LPC node
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* @dev: PCH PCI device containing the LPC
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* @return 0 if OK, -ve on error
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*/
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int lpc_early_init(const void *blob, int node, pci_dev_t dev);
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#endif
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