mirror of
https://github.com/AsahiLinux/u-boot
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a2ac2b964b
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
389 lines
9.7 KiB
C
389 lines
9.7 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* board.c
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*
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* Board functions for TCL SL50 board
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*
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* Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
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*/
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <net.h>
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#include <serial.h>
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#include <spl.h>
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#include <asm/arch/cpu.h>
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#include <asm/arch/hardware.h>
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#include <asm/arch/omap.h>
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#include <asm/arch/ddr_defs.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/gpio.h>
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#include <asm/arch/mmc_host_def.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/mem.h>
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#include <asm/global_data.h>
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#include <asm/io.h>
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#include <asm/emif.h>
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#include <asm/gpio.h>
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#include <i2c.h>
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#include <miiphy.h>
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#include <cpsw.h>
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#include <power/tps65217.h>
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#include <power/tps65910.h>
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#include <env_internal.h>
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#include <watchdog.h>
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#include "board.h"
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DECLARE_GLOBAL_DATA_PTR;
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static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
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#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
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static const struct ddr_data ddr3_sl50_data = {
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.datardsratio0 = MT41K256M16HA125E_RD_DQS,
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.datawdsratio0 = MT41K256M16HA125E_WR_DQS,
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.datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
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.datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
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};
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static const struct cmd_control ddr3_sl50_cmd_ctrl_data = {
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.cmd0csratio = MT41K256M16HA125E_RATIO,
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.cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd1csratio = MT41K256M16HA125E_RATIO,
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.cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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.cmd2csratio = MT41K256M16HA125E_RATIO,
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.cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
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};
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static struct emif_regs ddr3_sl50_emif_reg_data = {
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.sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
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.ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
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.sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
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.sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
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.sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
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.zq_config = MT41K256M16HA125E_ZQ_CFG,
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.emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
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};
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#ifdef CONFIG_SPL_OS_BOOT
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int spl_start_uboot(void)
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{
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/* break into full u-boot on 'c' */
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if (serial_tstc() && serial_getc() == 'c')
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return 1;
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#ifdef CONFIG_SPL_ENV_SUPPORT
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env_init();
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env_load();
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if (env_get_yesno("boot_os") != 1)
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return 1;
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#endif
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return 0;
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}
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#endif
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#define OSC (V_OSCK/1000000)
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const struct dpll_params dpll_ddr_sl50 = {
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400, OSC-1, 1, -1, -1, -1, -1};
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void am33xx_spl_board_init(void)
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{
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int mpu_vdd;
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/* Get the frequency */
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dpll_mpu_opp100.m = am335x_get_efuse_mpu_max_freq(cdev);
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/* BeagleBone PMIC Code */
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int usb_cur_lim;
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if (i2c_probe(TPS65217_CHIP_PM))
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return;
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/*
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* Increase USB current limit to 1300mA or 1800mA and set
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* the MPU voltage controller as needed.
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*/
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if (dpll_mpu_opp100.m == MPUPLL_M_1000) {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1800MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1325MV;
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} else {
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usb_cur_lim = TPS65217_USB_INPUT_CUR_LIMIT_1300MA;
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mpu_vdd = TPS65217_DCDC_VOLT_SEL_1275MV;
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}
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_NONE,
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TPS65217_POWER_PATH,
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usb_cur_lim,
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TPS65217_USB_INPUT_CUR_LIMIT_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set DCDC3 (CORE) voltage to 1.125V */
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if (tps65217_voltage_update(TPS65217_DEFDCDC3,
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TPS65217_DCDC_VOLT_SEL_1125MV)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/* Set CORE Frequencies to OPP100 */
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do_setup_dpll(&dpll_core_regs, &dpll_core_opp100);
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/* Set DCDC2 (MPU) voltage */
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if (tps65217_voltage_update(TPS65217_DEFDCDC2, mpu_vdd)) {
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puts("tps65217_voltage_update failure\n");
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return;
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}
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/*
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* Set LDO3 to 1.8V and LDO4 to 3.3V
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*/
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS1,
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TPS65217_LDO_VOLTAGE_OUT_1_8,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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if (tps65217_reg_write(TPS65217_PROT_LEVEL_2,
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TPS65217_DEFLS2,
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TPS65217_LDO_VOLTAGE_OUT_3_3,
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TPS65217_LDO_MASK))
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puts("tps65217_reg_write failure\n");
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/* Set MPU Frequency to what we detected now that voltages are set */
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do_setup_dpll(&dpll_mpu_regs, &dpll_mpu_opp100);
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}
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const struct dpll_params *get_dpll_ddr_params(void)
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{
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enable_i2c0_pin_mux();
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i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
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return &dpll_ddr_sl50;
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}
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void set_uart_mux_conf(void)
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{
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#if CONFIG_CONS_INDEX == 1
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enable_uart0_pin_mux();
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#elif CONFIG_CONS_INDEX == 2
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enable_uart1_pin_mux();
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#elif CONFIG_CONS_INDEX == 3
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enable_uart2_pin_mux();
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#elif CONFIG_CONS_INDEX == 4
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enable_uart3_pin_mux();
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#elif CONFIG_CONS_INDEX == 5
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enable_uart4_pin_mux();
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#elif CONFIG_CONS_INDEX == 6
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enable_uart5_pin_mux();
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#endif
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}
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void set_mux_conf_regs(void)
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{
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enable_board_pin_mux();
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}
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const struct ctrl_ioregs ioregs_evmsk = {
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.cm0ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.cm1ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.cm2ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.dt0ioctl = MT41J128MJT125_IOCTRL_VALUE,
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.dt1ioctl = MT41J128MJT125_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs_bonelt = {
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.cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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.dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs_evm15 = {
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.cm0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.cm1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.cm2ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.dt0ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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.dt1ioctl = MT41J512M8RH125_IOCTRL_VALUE,
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};
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const struct ctrl_ioregs ioregs = {
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.cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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.dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
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};
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void sdram_init(void)
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{
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config_ddr(400, &ioregs_bonelt,
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&ddr3_sl50_data,
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&ddr3_sl50_cmd_ctrl_data,
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&ddr3_sl50_emif_reg_data, 0);
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}
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#endif
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/*
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* Basic board specific setup. Pinmux has been handled already.
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*/
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int board_init(void)
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{
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#if defined(CONFIG_HW_WATCHDOG)
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hw_watchdog_init();
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#endif
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gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
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return 0;
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}
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#ifdef CONFIG_BOARD_LATE_INIT
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int board_late_init(void)
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{
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return 0;
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}
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#endif
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
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static void cpsw_control(int enabled)
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{
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/* VTP can be added here */
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return;
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}
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static struct cpsw_slave_data cpsw_slaves[] = {
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{
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.slave_reg_ofs = 0x208,
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.sliver_reg_ofs = 0xd80,
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.phy_addr = 0,
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},
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{
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.slave_reg_ofs = 0x308,
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.sliver_reg_ofs = 0xdc0,
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.phy_addr = 1,
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},
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};
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static struct cpsw_platform_data cpsw_data = {
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.mdio_base = CPSW_MDIO_BASE,
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.cpsw_base = CPSW_BASE,
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.mdio_div = 0xff,
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.channels = 8,
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.cpdma_reg_ofs = 0x800,
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.slaves = 1,
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.slave_data = cpsw_slaves,
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.ale_reg_ofs = 0xd00,
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.ale_entries = 1024,
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.host_port_reg_ofs = 0x108,
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.hw_stats_reg_ofs = 0x900,
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.bd_ram_ofs = 0x2000,
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.mac_control = (1 << 5),
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.control = cpsw_control,
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.host_port_num = 0,
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.version = CPSW_CTRL_VERSION_2,
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};
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#endif
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/*
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* This function will:
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* Read the eFuse for MAC addresses, and set ethaddr/eth1addr/usbnet_devaddr
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* in the environment
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* Perform fixups to the PHY present on certain boards. We only need this
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* function in:
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* - SPL with either CPSW or USB ethernet support
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* - Full U-Boot, with either CPSW or USB ethernet
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* Build in only these cases to avoid warnings about unused variables
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* when we build an SPL that has neither option but full U-Boot will.
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*/
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#if ((defined(CONFIG_SPL_ETH) || defined(CONFIG_SPL_USB_ETHER)) \
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&& defined(CONFIG_SPL_BUILD)) || \
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((defined(CONFIG_DRIVER_TI_CPSW) || \
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defined(CONFIG_USB_ETHER) && defined(CONFIG_MUSB_GADGET)) && \
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!defined(CONFIG_SPL_BUILD))
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int board_eth_init(struct bd_info *bis)
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{
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int rv, n = 0;
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uint8_t mac_addr[6];
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uint32_t mac_hi, mac_lo;
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/* try reading mac address from efuse */
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mac_lo = readl(&cdev->macid0l);
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mac_hi = readl(&cdev->macid0h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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#if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
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(defined(CONFIG_SPL_ETH) && defined(CONFIG_SPL_BUILD))
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if (!env_get("ethaddr")) {
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printf("<ethaddr> not set. Validating first E-fuse MAC\n");
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("ethaddr", mac_addr);
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}
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#ifdef CONFIG_DRIVER_TI_CPSW
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mac_lo = readl(&cdev->macid1l);
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mac_hi = readl(&cdev->macid1h);
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mac_addr[0] = mac_hi & 0xFF;
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mac_addr[1] = (mac_hi & 0xFF00) >> 8;
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mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
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mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
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mac_addr[4] = mac_lo & 0xFF;
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mac_addr[5] = (mac_lo & 0xFF00) >> 8;
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if (!env_get("eth1addr")) {
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if (is_valid_ethaddr(mac_addr))
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eth_env_set_enetaddr("eth1addr", mac_addr);
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}
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writel(MII_MODE_ENABLE, &cdev->miisel);
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cpsw_slaves[0].phy_if = cpsw_slaves[1].phy_if =
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PHY_INTERFACE_MODE_MII;
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rv = cpsw_register(&cpsw_data);
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if (rv < 0)
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printf("Error %d registering CPSW switch\n", rv);
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else
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n += rv;
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#endif
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/*
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*
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* CPSW RGMII Internal Delay Mode is not supported in all PVT
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* operating points. So we must set the TX clock delay feature
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* in the AR8051 PHY. Since we only support a single ethernet
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* device in U-Boot, we only do this for the first instance.
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*/
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#define AR8051_PHY_DEBUG_ADDR_REG 0x1d
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#define AR8051_PHY_DEBUG_DATA_REG 0x1e
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#define AR8051_DEBUG_RGMII_CLK_DLY_REG 0x5
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#define AR8051_RGMII_TX_CLK_DLY 0x100
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#endif
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#if defined(CONFIG_USB_ETHER) && \
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(!defined(CONFIG_SPL_BUILD) || defined(CONFIG_SPL_USB_ETHER))
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if (is_valid_ether_addr(mac_addr))
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eth_env_set_enetaddr("usbnet_devaddr", mac_addr);
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rv = usb_eth_initialize(bis);
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if (rv < 0)
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printf("Error %d registering USB_ETHER\n", rv);
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else
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n += rv;
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#endif
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return n;
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}
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#endif
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