mirror of
https://github.com/AsahiLinux/u-boot
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29f3e3f248
Convert TEGRA20_ defines to either TEGRA_ or NV_PA_ where appropriate. Convert tegra20_ source file and function names to tegra_, also. Upcoming Tegra30 port will use common code/defines/names where possible. Signed-off-by: Tom Warren <twarren@nvidia.com> Acked-by: Stephen Warren <swarren@nvidia.com>
146 lines
3.2 KiB
C
146 lines
3.2 KiB
C
/*
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* (C) Copyright 2010,2011
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* NVIDIA Corporation <www.nvidia.com>
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <asm/io.h>
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#include <asm/arch/clock.h>
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#include <asm/arch/funcmux.h>
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#include <asm/arch/pmc.h>
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#include <asm/arch/sys_proto.h>
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#include <asm/arch/tegra20.h>
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#include <asm/arch/warmboot.h>
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DECLARE_GLOBAL_DATA_PTR;
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enum {
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/* UARTs which we can enable */
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UARTA = 1 << 0,
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UARTB = 1 << 1,
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UARTD = 1 << 3,
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UART_COUNT = 4,
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};
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/*
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* Boot ROM initializes the odmdata in APBDEV_PMC_SCRATCH20_0,
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* so we are using this value to identify memory size.
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*/
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unsigned int query_sdram_size(void)
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{
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struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
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u32 reg;
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reg = readl(&pmc->pmc_scratch20);
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debug("pmc->pmc_scratch20 (ODMData) = 0x%08x\n", reg);
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/* bits 31:28 in OdmData are used for RAM size */
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switch ((reg) >> 28) {
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case 1:
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return 0x10000000; /* 256 MB */
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case 2:
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default:
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return 0x20000000; /* 512 MB */
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case 3:
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return 0x40000000; /* 1GB */
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}
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}
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int dram_init(void)
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{
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/* We do not initialise DRAM here. We just query the size */
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gd->ram_size = query_sdram_size();
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return 0;
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}
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#ifdef CONFIG_DISPLAY_BOARDINFO
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int checkboard(void)
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{
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printf("Board: %s\n", sysinfo.board_string);
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return 0;
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}
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#endif /* CONFIG_DISPLAY_BOARDINFO */
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static int uart_configs[] = {
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#if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
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FUNCMUX_UART1_UAA_UAB,
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#elif defined(CONFIG_TEGRA_UARTA_GPU)
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FUNCMUX_UART1_GPU,
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#elif defined(CONFIG_TEGRA_UARTA_SDIO1)
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FUNCMUX_UART1_SDIO1,
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#else
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FUNCMUX_UART1_IRRX_IRTX,
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#endif
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FUNCMUX_UART2_IRDA,
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-1,
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FUNCMUX_UART4_GMC,
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-1,
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};
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/**
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* Set up the specified uarts
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*
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* @param uarts_ids Mask containing UARTs to init (UARTx)
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*/
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static void setup_uarts(int uart_ids)
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{
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static enum periph_id id_for_uart[] = {
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PERIPH_ID_UART1,
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PERIPH_ID_UART2,
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PERIPH_ID_UART3,
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PERIPH_ID_UART4,
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};
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size_t i;
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for (i = 0; i < UART_COUNT; i++) {
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if (uart_ids & (1 << i)) {
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enum periph_id id = id_for_uart[i];
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funcmux_select(id, uart_configs[i]);
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clock_ll_start_uart(id);
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}
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}
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}
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void board_init_uart_f(void)
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{
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int uart_ids = 0; /* bit mask of which UART ids to enable */
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#ifdef CONFIG_TEGRA_ENABLE_UARTA
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uart_ids |= UARTA;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTB
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uart_ids |= UARTB;
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#endif
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#ifdef CONFIG_TEGRA_ENABLE_UARTD
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uart_ids |= UARTD;
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#endif
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setup_uarts(uart_ids);
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}
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#ifndef CONFIG_SYS_DCACHE_OFF
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void enable_caches(void)
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{
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/* Enable D-cache. I-cache is already enabled in start.S */
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dcache_enable();
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}
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#endif
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