mirror of
https://github.com/AsahiLinux/u-boot
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285aea01d2
To support HDMI display on EVK board, the LCDIF pix clock must be 25.2Mhz. Since the its PCC divider range is from 1-8, the max rate of LCDIF PCC source clock is 201.6Mhz. This limits the source clock must from NIC1 bus clock or NIC1 clock, other sources from APLL PFDs are higher than this max rate. The NIC1 bus clock and NIC1 clock are from DDRCLK whose parent source is APLL PFD0, so we must change the APLL PFD0 and have impact to DDRCLK, NIC1 and NIC1 bus. Eventually, this requests to set the APLL PFD0 frequency to 302.4Mhz (25.2 * 12), with settings: PFD0 FRAC: 32 APLL MULT: 22 APLL NUM: 2 APLL DENOM: 5 Signed-off-by: Ye Li <ye.li@nxp.com> Tested-by: Fancy Fang <chen.fang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
131 lines
3.2 KiB
INI
131 lines
3.2 KiB
INI
/* SPDX-License-Identifier: GPL-2.0+ */
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/*
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* Copyright (C) 2016 Freescale Semiconductor, Inc.
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*
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* Refer docs/README.imxmage for more details about how-to configure
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* and create imximage boot image
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*
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* The syntax is taken as close as possible with the kwbimage
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*/
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#define __ASSEMBLY__
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#include <config.h>
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/* image version */
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IMAGE_VERSION 2
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/*
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* Boot Device : one of
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* spi/sd/nand/onenand, qspi/nor
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*/
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BOOT_FROM sd
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#ifdef CONFIG_USE_IMXIMG_PLUGIN
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/*PLUGIN plugin-binary-file IRAM_FREE_START_ADDR*/
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PLUGIN board/freescale/mx7ulp_evk/plugin.bin 0x2F020000
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#else
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#ifdef CONFIG_SECURE_BOOT
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CSF CONFIG_CSF_SIZE
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#endif
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/*
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* Device Configuration Data (DCD)
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*
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* Each entry must have the format:
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* Addr-type Address Value
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*
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* where:
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* Addr-type register length (1,2 or 4 bytes)
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* Address absolute address of the register
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* value value to be stored in the register
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*/
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DATA 4 0x403f00dc 0x00000000
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DATA 4 0x403e0040 0x01000020
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DATA 4 0x403e0500 0x01000000
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DATA 4 0x403e050c 0x80808080
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DATA 4 0x403e0508 0x00160000
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DATA 4 0x403E0510 0x00000002
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DATA 4 0x403E0514 0x00000005
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DATA 4 0x403e0500 0x00000001
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CHECK_BITS_SET 4 0x403e0500 0x01000000
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DATA 4 0x403e050c 0x80808020
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CHECK_BITS_SET 4 0x403e050c 0x00000040
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DATA 4 0x403E0030 0x00000001
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DATA 4 0x403e0040 0x11000020
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DATA 4 0x403f00dc 0x42000000
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DATA 4 0x40B300AC 0x40000000
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DATA 4 0x40AD0128 0x00040000
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DATA 4 0x40AD00F8 0x00000000
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DATA 4 0x40AD00D8 0x00000180
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DATA 4 0x40AD0108 0x00000180
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DATA 4 0x40AD0104 0x00000180
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DATA 4 0x40AD0124 0x00010000
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DATA 4 0x40AD0080 0x0000018C
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DATA 4 0x40AD0084 0x0000018C
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DATA 4 0x40AD0088 0x0000018C
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DATA 4 0x40AD008C 0x0000018C
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DATA 4 0x40AD0120 0x00010000
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DATA 4 0x40AD010C 0x00000180
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DATA 4 0x40AD0110 0x00000180
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DATA 4 0x40AD0114 0x00000180
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DATA 4 0x40AD0118 0x00000180
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DATA 4 0x40AD0090 0x00000180
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DATA 4 0x40AD0094 0x00000180
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DATA 4 0x40AD0098 0x00000180
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DATA 4 0x40AD009C 0x00000180
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DATA 4 0x40AD00E0 0x00040000
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DATA 4 0x40AD00E4 0x00040000
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DATA 4 0x40AB001C 0x00008000
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DATA 4 0x40AB0800 0xA1390003
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DATA 4 0x40AB085C 0x0D3900A0
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DATA 4 0x40AB0890 0x00400000
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DATA 4 0x40AB0848 0x40404040
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DATA 4 0x40AB0850 0x40404040
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DATA 4 0x40AB081C 0x33333333
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DATA 4 0x40AB0820 0x33333333
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DATA 4 0x40AB0824 0x33333333
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DATA 4 0x40AB0828 0x33333333
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DATA 4 0x40AB08C0 0x24922492
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DATA 4 0x40AB08B8 0x00000800
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DATA 4 0x40AB0004 0x00020052
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DATA 4 0x40AB000C 0x292C42F3
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DATA 4 0x40AB0010 0x00100A22
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DATA 4 0x40AB0038 0x00120556
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DATA 4 0x40AB0014 0x00C700DB
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DATA 4 0x40AB0018 0x00211718
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DATA 4 0x40AB002C 0x0F9F26D2
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DATA 4 0x40AB0030 0x009F0E10
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DATA 4 0x40AB0040 0x0000003F
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DATA 4 0x40AB0000 0xC3190000
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DATA 4 0x40AB001C 0x00008010
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DATA 4 0x40AB001C 0x00008018
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DATA 4 0x40AB001C 0x003F8030
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DATA 4 0x40AB001C 0x003F8038
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DATA 4 0x40AB001C 0xFF0A8030
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DATA 4 0x40AB001C 0xFF0A8038
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DATA 4 0x40AB001C 0x04028030
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DATA 4 0x40AB001C 0x04028038
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DATA 4 0x40AB001C 0x83018030
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DATA 4 0x40AB001C 0x83018038
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DATA 4 0x40AB001C 0x01038030
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DATA 4 0x40AB001C 0x01038038
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DATA 4 0x40AB083C 0x20000000
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DATA 4 0x40AB0020 0x00001800
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DATA 4 0x40AB0800 0xA1310000
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DATA 4 0x40AB0004 0x00020052
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DATA 4 0x40AB0404 0x00011006
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DATA 4 0x40AB001C 0x00000000
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#endif
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