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d2170168dd
Rename Stratix10 FPGA driver to Intel FPGA SDM Mailbox driver because it is using generic SDM (Secure Device Manager) Mailbox interface shared by other platform (e.g. Agilex) as well. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
89 lines
1.7 KiB
C
89 lines
1.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
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*
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*/
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#include <altera.h>
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#include <common.h>
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#include <env.h>
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#include <errno.h>
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#include <init.h>
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#include <log.h>
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#include <asm/io.h>
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#include <asm/arch/mailbox_s10.h>
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#include <asm/arch/misc.h>
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#include <asm/arch/reset_manager.h>
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#include <asm/arch/system_manager.h>
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DECLARE_GLOBAL_DATA_PTR;
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/*
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* FPGA programming support for SoC FPGA Stratix 10
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*/
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static Altera_desc altera_fpga[] = {
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{
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/* Family */
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Intel_FPGA_SDM_Mailbox,
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/* Interface type */
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secure_device_manager_mailbox,
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/* No limitation as additional data will be ignored */
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-1,
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/* No device function table */
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NULL,
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/* Base interface address specified in driver */
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NULL,
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/* No cookie implementation */
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0
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},
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};
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/*
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* Print CPU information
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*/
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#if defined(CONFIG_DISPLAY_CPUINFO)
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int print_cpuinfo(void)
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{
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puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
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return 0;
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}
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#endif
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#ifdef CONFIG_ARCH_MISC_INIT
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int arch_misc_init(void)
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{
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char qspi_string[13];
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sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
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env_set("qspi_clock", qspi_string);
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return 0;
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}
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#endif
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int arch_early_init_r(void)
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{
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socfpga_fpga_add(&altera_fpga[0]);
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return 0;
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}
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/* Return 1 if FPGA is ready otherwise return 0 */
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int is_fpga_config_ready(void)
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{
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return (readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_FPGA_CONFIG) &
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SYSMGR_FPGACONFIG_READY_MASK) == SYSMGR_FPGACONFIG_READY_MASK;
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}
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void do_bridge_reset(int enable, unsigned int mask)
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{
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/* Check FPGA status before bridge enable */
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if (!is_fpga_config_ready()) {
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puts("FPGA not ready. Bridge reset aborted!\n");
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return;
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}
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socfpga_bridges_reset(enable);
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}
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