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6f6fbb334c
In both the Freescale DDR controller and the SPD spec, bank address bits
are stored as the number of bank address bits minus 2. For example, if a
chip had 8 banks (3 total bank address bits), the value of
bank_addr_bits would be 1. This is rather surprising for users
configuring their memory manually, since they can't set bank_addr_bits
to the actual number of bank address bits. Rectify this.
There is at least one example of this kind of mistake already, in
board/freescale/t102xrdb/ddr.c. The documented MT40A512M8HX has two bank
address bits, but bank_addr_bits was set to 2, implying 4 bank address
bits. Such a value is reserved in BA_BITS_CS, but I suspect the
controller simply ignores the top bit, making this kind of mistake
harmless, if misleading.
Fixes:
|
||
|---|---|---|
| .. | ||
| arm_ddr_gen3.c | ||
| ctrl_regs.c | ||
| ddr1_dimm_params.c | ||
| ddr2_dimm_params.c | ||
| ddr3_dimm_params.c | ||
| ddr4_dimm_params.c | ||
| fsl_ddr_gen4.c | ||
| fsl_mmdc.c | ||
| interactive.c | ||
| Kconfig | ||
| lc_common_dimm_params.c | ||
| main.c | ||
| Makefile | ||
| mpc85xx_ddr_gen1.c | ||
| mpc85xx_ddr_gen2.c | ||
| mpc85xx_ddr_gen3.c | ||
| options.c | ||
| util.c | ||