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u-boot/arch/arm/mach-socfpga/include/mach/system_manager_gen5.h
Ralph Siemsen b0b08ce0b7 arm: socfpga: fix Gen5 enable of EMAC via FPGA
An earlier conversion from struct to defines introduced two errors, both
related to setup of EMAC routed via the FPGA. One of the offsets was
incorrect, and the EMAC0/EMAC1 were swapped.

The effect of this was rather odd: both ports could operate at gigabit,
but one of them would fail to transmit when operating at 100Mbit.

Fixes: db5741f7a8 ("arm: socfpga: Convert system manager from struct to defines")

Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
2020-10-21 11:45:54 +08:00

44 lines
1.3 KiB
C

/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright (C) 2013-2017 Altera Corporation <www.altera.com>
*/
#ifndef _SYSTEM_MANAGER_GEN5_H_
#define _SYSTEM_MANAGER_GEN5_H_
#ifndef __ASSEMBLY__
void sysmgr_pinmux_init(void);
void sysmgr_config_warmrstcfgio(int enable);
void sysmgr_get_pinmux_table(const u8 **table, unsigned int *table_len);
#define SYSMGR_GEN5_WDDBG 0x10
#define SYSMGR_GEN5_BOOTINFO 0x14
#define SYSMGR_GEN5_FPGAINFGRP_GBL 0x20
#define SYSMGR_GEN5_FPGAINFGRP_INDIV 0x24
#define SYSMGR_GEN5_FPGAINFGRP_MODULE 0x28
#define SYSMGR_GEN5_SCANMGRGRP_CTRL 0x30
#define SYSMGR_GEN5_ISWGRP_HANDOFF 0x80
#define SYSMGR_GEN5_ROMCODEGRP_CTRL 0xc0
#define SYSMGR_GEN5_WARMRAMGRP_EN 0xe0
#define SYSMGR_GEN5_SDMMC 0x108
#define SYSMGR_GEN5_ECCGRP_OCRAM 0x144
#define SYSMGR_GEN5_EMACIO 0x400
#define SYSMGR_GEN5_NAND_USEFPGA 0x6f0
#define SYSMGR_GEN5_RGMII1_USEFPGA 0x6f8
#define SYSMGR_GEN5_SDMMC_USEFPGA 0x708
#define SYSMGR_GEN5_RGMII0_USEFPGA 0x714
#define SYSMGR_GEN5_SPIM1_USEFPGA 0x730
#define SYSMGR_GEN5_SPIM0_USEFPGA 0x738
#define SYSMGR_SDMMC SYSMGR_GEN5_SDMMC
#define SYSMGR_ISWGRP_HANDOFF_OFFSET(i) \
SYSMGR_GEN5_ISWGRP_HANDOFF + ((i) * sizeof(u32))
#endif
#define SYSMGR_SDMMC_SMPLSEL_SHIFT 3
#define SYSMGR_BOOTINFO_BSEL_SHIFT 0
#endif /* _SYSTEM_MANAGER_GEN5_H_ */