Akshay Saraswat 234370cab4 Exynos5: clock: Update the equation to calculate PLL output frequency ... According to the latest exynos5 user manual, the equation for calculating PLL output was changed to FOUT= MDIV x FIN/(PDIV x 2^SDIV) earlier it was FOUT= MDIV x FIN/(PDIV x 2^(SDIV -1)) So updating the clock code accordingly. Signed-off-by: Hatim Ali <hatim.rv@samsung.com> Signed-off-by: Akshay Saraswat <akshay.s@samsung.com> Acked-by: Simon Glass <sjg@chromium.org> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>		2013-05-21 20:17:30 +09:00
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clock.c	Exynos5: clock: Update the equation to calculate PLL output frequency	2013-05-21 20:17:30 +09:00
Makefile	EXYNOS5: PINMUX: Added default pinumx settings	2012-07-07 14:07:25 +02:00
pinmux.c	EXYNOS5: FDT : Decode peripheral id	2013-01-08 10:54:32 +09:00
power.c	Exynos5: TMU: Add hardware tripping	2013-03-12 17:07:31 +09:00
soc.c	EXYNOS5: Add L2 Cache Support.	2013-03-27 16:53:37 +09:00
system.c	EXYNOS5: support display system register control	2012-09-01 14:58:24 +02:00