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The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com> |
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| .. | ||
| at32ap700x | ||
| cache.c | ||
| config.mk | ||
| cpu.c | ||
| exception.c | ||
| hsdramc.c | ||
| hsdramc1.h | ||
| hsmc3.h | ||
| interrupts.c | ||
| Makefile | ||
| pio.c | ||
| pio2.h | ||
| start.S | ||