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https://github.com/AsahiLinux/u-boot
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avr32: Use the same entry point for reset and exception handling
Since the reset vector is always aligned to a very large boundary, we can save a couple of KB worth of alignment padding by placing the exception vectors at the same address. Deciding which one it is is easy: If we're handling an exception, the CPU is in Exception mode. If we're starting up after reset, the CPU is in Supervisor mode. So this adds a very minimal overhead to the reset path (only executed once) and the exception handling path (normally never executed at all.) Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
This commit is contained in:
Haavard Skinnemoen
parent
0c16eed218
commit
caf83ea888
5 changed files with 122 additions and 74 deletions
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@ -29,6 +29,7 @@ SECTIONS
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. = 0;
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_text = .;
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.text : {
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*(.exception.text)
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*(.text)
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*(.text.*)
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}
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@ -29,6 +29,7 @@ SECTIONS
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. = 0;
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_text = .;
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.text : {
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*(.exception.text)
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*(.text)
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*(.text.*)
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}
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@ -29,7 +29,6 @@ LIB := $(obj)lib$(CPU).a
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START-y += start.o
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SOBJS-y += entry.o
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COBJS-y += cpu.o
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COBJS-y += hsdramc.o
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COBJS-y += exception.o
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@ -1,64 +0,0 @@
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/*
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* Copyright (C) 2004-2006 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <asm/sysreg.h>
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#include <asm/ptrace.h>
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.section .text.exception,"ax"
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.global _evba
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.type _evba,@function
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.align 10
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_evba:
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.irp x,0,1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16
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.align 2
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rjmp unknown_exception
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.endr
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.global timer_interrupt_handler
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.type timer_interrupt_handler,@function
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.align 2
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timer_interrupt_handler:
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/*
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* Increment timer_overflow and re-write COMPARE with 0xffffffff.
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*
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* We're running at interrupt level 3, so we don't need to save
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* r8-r12 or lr to the stack.
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*/
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lda.w r8, timer_overflow
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ld.w r9, r8[0]
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mov r10, -1
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mtsr SYSREG_COMPARE, r10
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sub r9, -1
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st.w r8[0], r9
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rete
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.type unknown_exception, @function
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unknown_exception:
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pushm r0-r12
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sub r8, sp, REG_R12 - REG_R0 - 4
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mov r9, lr
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mfsr r10, SYSREG_RAR_EX
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mfsr r11, SYSREG_RSR_EX
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pushm r8-r11
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_unknown_exception
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1: rjmp 1b
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2005-2006 Atmel Corporation
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* Copyright (C) 2005-2008 Atmel Corporation
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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@ -20,12 +20,9 @@
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* MA 02111-1307 USA
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*/
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#include <config.h>
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#include <asm/ptrace.h>
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#include <asm/sysreg.h>
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#ifndef PART_SPECIFIC_BOOTSTRAP
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# define PART_SPECIFIC_BOOTSTRAP
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#endif
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#define SYSREG_MMUCR_I_OFFSET 2
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#define SYSREG_MMUCR_S_OFFSET 4
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@ -34,11 +31,115 @@
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| SYSREG_BIT(FE) | SYSREG_BIT(RE) \
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| SYSREG_BIT(IBE) | SYSREG_BIT(IEE))
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.text
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/*
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* To save some space, we use the same entry point for
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* exceptions and reset. This avoids lots of alignment padding
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* since the reset vector is always suitably aligned.
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*/
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.section .exception.text, "ax", @progbits
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.global _start
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.global _evba
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.type _start, @function
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.type _evba, @function
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_start:
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PART_SPECIFIC_BOOTSTRAP
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.size _start, 0
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_evba:
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.org 0x00
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rjmp unknown_exception /* Unrecoverable exception */
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.org 0x04
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rjmp unknown_exception /* TLB multiple hit */
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.org 0x08
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rjmp unknown_exception /* Bus error data fetch */
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.org 0x0c
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rjmp unknown_exception /* Bus error instruction fetch */
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.org 0x10
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rjmp unknown_exception /* NMI */
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.org 0x14
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rjmp unknown_exception /* Instruction address */
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.org 0x18
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rjmp unknown_exception /* ITLB protection */
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.org 0x1c
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rjmp unknown_exception /* Breakpoint */
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.org 0x20
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rjmp unknown_exception /* Illegal opcode */
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.org 0x24
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rjmp unknown_exception /* Unimplemented instruction */
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.org 0x28
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rjmp unknown_exception /* Privilege violation */
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.org 0x2c
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rjmp unknown_exception /* Floating-point */
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.org 0x30
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rjmp unknown_exception /* Coprocessor absent */
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.org 0x34
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rjmp unknown_exception /* Data Address (read) */
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.org 0x38
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rjmp unknown_exception /* Data Address (write) */
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.org 0x3c
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rjmp unknown_exception /* DTLB Protection (read) */
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.org 0x40
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rjmp unknown_exception /* DTLB Protection (write) */
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.org 0x44
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rjmp unknown_exception /* DTLB Modified */
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.org 0x50
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rjmp unknown_exception /* ITLB Miss */
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.org 0x60
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rjmp unknown_exception /* DTLB Miss (read) */
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.org 0x70
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rjmp unknown_exception /* DTLB Miss (write) */
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.size _evba, . - _evba
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.align 2
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.type unknown_exception, @function
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unknown_exception:
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/* Figure out whether we're handling an exception (Exception
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* mode) or just booting (Supervisor mode). */
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csrfcz SYSREG_M1_OFFSET
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brcc at32ap_cpu_bootstrap
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/* This is an exception. Complain. */
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pushm r0-r12
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sub r8, sp, REG_R12 - REG_R0 - 4
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mov r9, lr
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mfsr r10, SYSREG_RAR_EX
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mfsr r11, SYSREG_RSR_EX
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pushm r8-r11
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mfsr r12, SYSREG_ECR
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mov r11, sp
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rcall do_unknown_exception
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1: rjmp 1b
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/* The COUNT/COMPARE timer interrupt handler */
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.global timer_interrupt_handler
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.type timer_interrupt_handler,@function
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.align 2
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timer_interrupt_handler:
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/*
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* Increment timer_overflow and re-write COMPARE with 0xffffffff.
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*
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* We're running at interrupt level 3, so we don't need to save
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* r8-r12 or lr to the stack.
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*/
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lda.w r8, timer_overflow
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ld.w r9, r8[0]
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mov r10, -1
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mtsr SYSREG_COMPARE, r10
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sub r9, -1
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st.w r8[0], r9
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rete
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/*
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* CPU bootstrap after reset is handled here. SoC code may
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* override this in case they need to initialize oscillators,
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* etc.
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*/
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.section .text.at32ap_cpu_bootstrap, "ax", @progbits
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.global at32ap_cpu_bootstrap
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.weak at32ap_cpu_bootstrap
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.type at32ap_cpu_bootstrap, @function
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.align 2
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at32ap_cpu_bootstrap:
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/* Reset the Status Register */
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mov r0, lo(SR_INIT)
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orh r0, hi(SR_INIT)
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@ -66,9 +167,16 @@ _start:
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lddpc pc, 1f
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.align 2
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1: .long 2f
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1: .long at32ap_low_level_init
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.size _start, . - _start
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2: lddpc sp, sp_init
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/* Common CPU bootstrap code after oscillator/cache/etc. init */
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.section .text.avr32ap_low_level_init, "ax", @progbits
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.global at32ap_low_level_init
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.type at32ap_low_level_init, @function
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.align 2
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at32ap_low_level_init:
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lddpc sp, sp_init
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/* Initialize the GOT pointer */
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lddpc r6, got_init
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@ -90,6 +198,7 @@ got_init:
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* Relocate the u-boot image into RAM and continue from there.
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* Does not return.
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*/
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.section .text.relocate_code,"ax",@progbits
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.global relocate_code
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.type relocate_code,@function
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relocate_code:
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@ -162,3 +271,5 @@ in_ram:
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.align 2
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got_init_reloc:
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.long 3b - _GLOBAL_OFFSET_TABLE_
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.size relocate_code, . - relocate_code
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