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u-boot/arch/arm/cpu
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Ran Wang 223c19076f fsl-layerscape: enable dwc3 snooping feature 
Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
2020-09-24 20:57:32 +05:30
..
arm11 common: Drop net.h from common header 2020-05-18 17:33:31 -04:00
arm720t rename symbol: CONFIG_TEGRA -> CONFIG_ARCH_TEGRA 2020-05-15 14:47:35 -04:00
arm920t common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
arm926ejs treewide: convert bd_t to struct bd_info by coccinelle 2020-07-17 09:30:13 -04:00
arm946es common: Move enable/disable_interrupts out of common.h 2019-12-02 18:25:01 -05:00
arm1136 treewide: convert bd_t to struct bd_info by coccinelle 2020-07-17 09:30:13 -04:00
arm1176 SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
armv7 ARM: add Kconfig option for PSCI 0.1 2020-08-05 08:18:34 -04:00
armv7m common: Drop linux/bitops.h from common header 2020-05-18 21:19:23 -04:00
armv8 fsl-layerscape: enable dwc3 snooping feature 2020-09-24 20:57:32 +05:30
pxa common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
sa1100 common: Drop linux/delay.h from common header 2020-05-18 21:19:23 -04:00
Makefile SPDX: Convert all of our single license tags to Linux Kernel style 2018-05-07 09:34:12 -04:00
u-boot-spl.lds spl: fix linker size check off-by-one errors 2019-05-05 08:48:50 -04:00
u-boot.lds ARM: Specify aligned address for secure section instead of using attributes 2018-09-07 09:11:42 -04:00