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fsl-layerscape: enable dwc3 snooping feature

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Configure DWC3’s cache type to ‘cacheable’ for better
performance. Actually related register definition and values are SoC
specific, which means this setting is only applicable to Layerscape SoC,
not generic for all platforms which have integrated DWC3 IP.

Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
This commit is contained in:
Ran Wang 2020-08-05 15:07:27 +08:00 committed by Priyanka Jain
parent b7585aa9b1
commit 223c19076f
1 changed files with 37 additions and 0 deletions
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37
arch/arm/cpu/armv8/fsl-layerscape/soc.c
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@ -36,6 +36,8 @@
#ifdef CONFIG_TFABOOT
#include <env_internal.h>
#endif
#include <dm.h>
#include <linux/err.h>
#if defined(CONFIG_TFABOOT) || defined(CONFIG_GIC_V3_ITS)
DECLARE_GLOBAL_DATA_PTR;
#endif
@ -897,6 +899,38 @@ __weak int fsl_board_late_init(void)
return 0;
}
#define DWC3_GSBUSCFG0 0xc100
#define DWC3_GSBUSCFG0_CACHETYPE_SHIFT 16
#define DWC3_GSBUSCFG0_CACHETYPE(n) (((n) & 0xffff) \
<< DWC3_GSBUSCFG0_CACHETYPE_SHIFT)
void enable_dwc3_snooping(void)
{
int ret;
u32 val;
struct udevice *bus;
struct uclass *uc;
fdt_addr_t dwc3_base;
ret = uclass_get(UCLASS_USB, &uc);
if (ret)
return;
uclass_foreach_dev(bus, uc) {
if (!strcmp(bus->driver->of_match->compatible, "fsl,layerscape-dwc3")) {
dwc3_base = devfdt_get_addr(bus);
if (dwc3_base == FDT_ADDR_T_NONE) {
dev_err(bus, "dwc3 regs missing\n");
continue;
}
val = in_le32(dwc3_base + DWC3_GSBUSCFG0);
val &= ~DWC3_GSBUSCFG0_CACHETYPE(~0);
val |= DWC3_GSBUSCFG0_CACHETYPE(0x2222);
writel(val, dwc3_base + DWC3_GSBUSCFG0);
}
}
}
int board_late_init(void)
{
#ifdef CONFIG_CHAIN_OF_TRUST
@ -934,6 +968,9 @@ int board_late_init(void)
fspi_ahb_init();
#endif
if (IS_ENABLED(CONFIG_DM))
enable_dwc3_snooping();
return fsl_board_late_init();
}
#endif