u-boot/board/matrix_vision/mvbc_p
Wolfgang Denk 702e6014f1 doc: cleanup - move board READMEs into respective board directories
Also drop a few files referring to no longer / not yet supported
boards.

Signed-off-by: Wolfgang Denk <wd@denx.de>
Cc: Prafulla Wadaskar <prafulla@marvell.com>
Cc: Stefan Roese <sr@denx.de>
Cc: Kim Phillips <kim.phillips@freescale.com>
Cc: Andy Fleming <afleming@gmail.com>
Cc: Jason Jin <jason.jin@freescale.com>
Cc: Stefano Babic <sbabic@denx.de>
Cc: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
Acked-by: Stefano Babic <sbabic@denx.de>
Acked-by: Daniel Schwierzeck <daniel.schwierzeck@googlemail.com>
2012-07-29 15:42:02 +02:00
..
fpga.c fpga: constify to fix build warning 2011-08-01 15:19:40 +02:00
fpga.h fpga: constify to fix build warning 2011-08-01 15:19:40 +02:00
Makefile punt unused clean/distclean targets 2011-10-15 22:20:36 +02:00
mvbc_p.c bootstage: Convert net progress numbers to enums 2012-03-18 21:33:05 +01:00
mvbc_p.h Use common code for Matrix Vision boards 2009-08-28 00:31:23 +02:00
mvbc_p_autoscript Remove deprecated 'autoscr' command/variables 2009-09-22 23:03:24 +02:00
README.mvbc_p doc: cleanup - move board READMEs into respective board directories 2012-07-29 15:42:02 +02:00

Matrix Vision mvBlueCOUGAR-P (mvBC-P)
-------------------------------------

1.	Board Description

	The mvBC-P is a 70x40x40mm multi board gigabit ethernet network camera
	with main focus on GigEVision protocol in combination with local image
	preprocessing.

	Power Supply is either VDC 48V or Pover over Ethernet (PoE).

2	System Components

2.1	CPU
	Freescale MPC5200B CPU running at 400MHz core and 133MHz XLB/IPB.
	64MB SDRAM @ 133MHz.
	8 MByte Nor Flash on local bus.
	1 serial ports. Console running on ttyS0 @ 115200 8N1.

2.2	PCI
	PCI clock fixed at 66MHz. Arbitration inside FPGA.
	Intel GD82541ER network MAC/PHY and FPGA connected.

2.3	FPGA
	Altera Cyclone-II EP2C8 with PCI DMA engine.
	Connects to Matrix Vision specific CCD/CMOS sensor interface.
	Utilizes 64MB Nand Flash.

2.3.1	I/O @ FPGA
	2 Outputs : photo coupler
	2 Inputs  : photo coupler

2.4	I2C
	LM75 @ 0x90 for temperature monitoring.
	EEPROM @ 0xA0 for vendor specifics.
	image sensor interface (slave addresses depend on sensor)

3	Flash layout.

	reset vector is 0x00000100, i.e. "LOWBOOT".

	FF800000	u-boot
	FF840000	u-boot script image
	FF850000	redundant u-boot script image
	FF860000	FPGA raw bit file
	FF8A0000	tbd.
	FF900000	root FS
	FFC00000	kernel
	FFFC0000	device tree blob
	FFFD0000	redundant device tree blob
	FFFE0000	environment
	FFFF0000	redundant environment

	mtd partitions are propagated to linux kernel via device tree blob.

4	Booting

	On startup the bootscript @ FF840000 is executed. This script can be
	exchanged easily. Default boot mode is "boot from flash", i.e. system
	works stand-alone.

	This behaviour depends on some environment variables :

	"netboot" : yes ->try dhcp/bootp and boot from network.
	A "dhcp_client_id" and "dhcp_vendor-class-identifier" can be used for
	DHCP server configuration, e.g. to provide different images to
	different devices.

	During netboot the system tries to get 3 image files:
	1. Kernel - name + data is given during BOOTP.
	2. Initrd - name is stored in "initrd_name"
	3. device tree blob - name is stored in "dtb_name"
	Fallback files are the flash versions.