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99d7b0a43d
On P204x/P304x/P50x0 Rev1.0, USB transmit will result in false internal multi-bit ECC errors, which has impact on performance, so software should disable all ECC reporting from USB1 and USB2. In formal release document, the errata number should be USB14 instead of USB138. Signed-off-by: xulei <Lei.Xu@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: xulei <B33228@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
268 lines
8.1 KiB
C
268 lines
8.1 KiB
C
/*
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* Copyright 2010-2011 Freescale Semiconductor, Inc.
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*
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* See file CREDITS for list of people who contributed to this
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* project.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
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* MA 02111-1307 USA
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*/
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#include <common.h>
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#include <command.h>
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#include <linux/compiler.h>
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#include <asm/processor.h>
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#include "fsl_corenet_serdes.h"
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
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/*
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* This work-around is implemented in PBI, so just check to see if the
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* work-around was actually applied. To do this, we check for specific data
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* at specific addresses in DCSR.
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*
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* Array offsets[] contains a list of offsets within DCSR. According to the
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* erratum document, the value at each offset should be 2.
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*/
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static void check_erratum_a4849(uint32_t svr)
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{
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void __iomem *dcsr = (void *)CONFIG_SYS_DCSRBAR + 0xb0000;
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unsigned int i;
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#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
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static const uint8_t offsets[] = {
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0x50, 0x54, 0x58, 0x90, 0x94, 0x98
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};
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#endif
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#ifdef CONFIG_PPC_P4080
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static const uint8_t offsets[] = {
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0x60, 0x64, 0x68, 0x6c, 0xa0, 0xa4, 0xa8, 0xac
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};
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#endif
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uint32_t x108; /* The value that should be at offset 0x108 */
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for (i = 0; i < ARRAY_SIZE(offsets); i++) {
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if (in_be32(dcsr + offsets[i]) != 2) {
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printf("Work-around for Erratum A004849 is not enabled\n");
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return;
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}
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}
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#if defined(CONFIG_PPC_P2041) || defined(CONFIG_PPC_P3041)
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x108 = 0x12;
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#endif
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#ifdef CONFIG_PPC_P4080
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/*
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* For P4080, the erratum document says that the value at offset 0x108
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* should be 0x12 on rev2, or 0x1c on rev3.
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*/
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if (SVR_MAJ(svr) == 2)
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x108 = 0x12;
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if (SVR_MAJ(svr) == 3)
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x108 = 0x1c;
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#endif
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if (in_be32(dcsr + 0x108) != x108) {
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printf("Work-around for Erratum A004849 is not enabled\n");
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return;
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}
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/* Everything matches, so the erratum work-around was applied */
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printf("Work-around for Erratum A004849 enabled\n");
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}
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
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/*
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* This work-around is implemented in PBI, so just check to see if the
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* work-around was actually applied. To do this, we check for specific data
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* at specific addresses in the SerDes register block.
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*
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* The work-around says that for each SerDes lane, write BnTTLCRy0 =
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* 0x1B00_0001, Register 2 = 0x0088_0000, and Register 3 = 0x4000_0000.
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*/
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static void check_erratum_a4580(uint32_t svr)
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{
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const serdes_corenet_t __iomem *srds_regs =
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(void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
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unsigned int lane;
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for (lane = 0; lane < SRDS_MAX_LANES; lane++) {
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if (serdes_lane_enabled(lane)) {
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const struct serdes_lane __iomem *srds_lane =
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&srds_regs->lane[serdes_get_lane_idx(lane)];
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/*
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* Verify that the values we were supposed to write in
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* the PBI are actually there. Also, the lower 15
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* bits of res4[3] should be the same as the upper 15
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* bits of res4[1].
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*/
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if ((in_be32(&srds_lane->ttlcr0) != 0x1b000001) ||
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(in_be32(&srds_lane->res4[1]) != 0x880000) ||
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(in_be32(&srds_lane->res4[3]) != 0x40000044)) {
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printf("Work-around for Erratum A004580 is "
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"not enabled\n");
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return;
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}
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}
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}
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/* Everything matches, so the erratum work-around was applied */
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printf("Work-around for Erratum A004580 enabled\n");
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}
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#endif
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static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
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{
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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extern int enable_cpu_a011_workaround;
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#endif
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__maybe_unused u32 svr = get_svr();
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#if defined(CONFIG_FSL_SATA_V2) && defined(CONFIG_FSL_SATA_ERRATUM_A001)
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if (IS_SVR_REV(svr, 1, 0)) {
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switch (SVR_SOC_VER(svr)) {
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case SVR_P1013:
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case SVR_P1022:
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puts("Work-around for Erratum SATA A001 enabled\n");
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}
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}
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES8)
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puts("Work-around for Erratum SERDES8 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES9)
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puts("Work-around for Erratum SERDES9 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_SERDES_A005)
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puts("Work-around for Erratum SERDES-A005 enabled\n");
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#endif
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#if defined(CONFIG_SYS_P4080_ERRATUM_CPU22)
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum CPU22 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011
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/*
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* NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in 3.0
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* also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1
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* The SVR has been checked by cpu_init_r().
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*/
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if (enable_cpu_a011_workaround)
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puts("Work-around for Erratum CPU-A011 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_CPU_A003999)
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puts("Work-around for Erratum CPU-A003999 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_A003474)
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puts("Work-around for Erratum DDR-A003473 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN)
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puts("Work-around for DDR MSYNC_IN Erratum enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC111)
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puts("Work-around for Erratum ESDHC111 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004468
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puts("Work-around for Erratum A004468 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC135)
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puts("Work-around for Erratum ESDHC135 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC13)
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if (SVR_MAJ(svr) < 3)
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puts("Work-around for Erratum ESDHC13 enabled\n");
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#endif
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#if defined(CONFIG_SYS_FSL_ERRATUM_ESDHC_A001)
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puts("Work-around for Erratum ESDHC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A002
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puts("Work-around for Erratum CPC-A002 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_CPC_A003
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puts("Work-around for Erratum CPC-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_ELBC_A001
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puts("Work-around for Erratum ELBC-A001 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_A003
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puts("Work-around for Erratum DDR-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR_115
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puts("Work-around for Erratum DDR115 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134
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puts("Work-around for Erratum DDR111 enabled\n");
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puts("Work-around for Erratum DDR134 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A002769
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puts("Work-around for Erratum IFC-A002769 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549
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puts("Work-around for Erratum P1010-A003549 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_IFC_A003399
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puts("Work-around for Erratum IFC A-003399 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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puts("Work-around for Erratum NMG DDR120 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_LBC103
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puts("Work-around for Erratum NMG_LBC103 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_ETSEC129
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if ((SVR_MAJ(svr) == 1) || IS_SVR_REV(svr, 2, 0))
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puts("Work-around for Erratum NMG ETSEC129 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004510
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puts("Work-around for Erratum A004510 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_SRIO_A004034
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puts("Work-around for Erratum SRIO-A004034 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A_004934
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puts("Work-around for Erratum A004934 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A005871
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if (IS_SVR_REV(svr, 1, 0))
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puts("Work-around for Erratum A005871 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004849
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/* This work-around is implemented in PBI, so just check for it */
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check_erratum_a4849(svr);
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_A004580
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/* This work-around is implemented in PBI, so just check for it */
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check_erratum_a4580(svr);
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#endif
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#ifdef CONFIG_SYS_P4080_ERRATUM_PCIE_A003
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puts("Work-around for Erratum PCIe-A003 enabled\n");
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#endif
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#ifdef CONFIG_SYS_FSL_ERRATUM_USB14
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puts("Work-around for Erratum USB14 enabled\n");
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#endif
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return 0;
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}
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U_BOOT_CMD(
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errata, 1, 0, do_errata,
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"Report errata workarounds",
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""
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);
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