..
altera_spi.c
spi: altera_spi: Minor cleanup
2015-10-28 13:54:09 +05:30
armada100_spi.c
Add GPL-2.0+ SPDX-License-Identifier to source files
2013-07-24 09:44:38 -04:00
atmel_dataflash_spi.c
spi: atmel_dataflash: Simplify AT91F_SpiEnable implementation
2014-03-17 21:54:57 +05:30
atmel_spi.c
Add GPL-2.0+ SPDX-License-Identifier to source files
2013-07-24 09:44:38 -04:00
atmel_spi.h
spi: atmel_spi: Use GENMASK
2015-10-27 23:21:42 +05:30
bfin_spi.c
blackfin: add spi and i2c specific get clock functions
2014-02-20 06:46:56 +01:00
bfin_spi6xx.c
spi: bfin_spi6xx: Use BIT macro
2015-10-27 23:19:29 +05:30
cadence_qspi.c
spi: cadence_qspi: Ensure check for max frequency in place
2015-11-05 02:34:15 +01:00
cadence_qspi.h
spi: cadence_qspi: Ensure spi_calibration is run when sclk change
2015-11-05 02:34:15 +01:00
cadence_qspi_apb.c
spi: cadence_qspi_apb: Use BIT macro
2015-10-27 23:19:29 +05:30
cf_qspi.c
spi: cf_qspi: fix clamp macro type check compilation warnings
2015-07-01 22:58:50 +05:30
cf_spi.c
spi: cf_spi: Staticize local functions
2015-03-30 01:42:49 +05:30
davinci_spi.c
bitops: introduce BIT() definition
2015-09-11 17:15:32 -04:00
designware_spi.c
spi: designware_spi: Use GENMASK
2015-10-27 23:21:43 +05:30
ep93xx_spi.c
bitops: introduce BIT() definition
2015-09-11 17:15:32 -04:00
exynos_spi.c
dm: Use dev_get_addr() where possible
2015-08-31 07:57:26 -06:00
fsl_dspi.c
spi: fsl: Use BIT macro
2015-10-27 23:19:29 +05:30
fsl_espi.c
spi: fsl: Use BIT macro
2015-10-27 23:19:29 +05:30
fsl_qspi.c
Merge branch 'master' of git://git.denx.de/u-boot-spi
2015-10-28 16:56:43 -04:00
fsl_qspi.h
qspi:fsl implement AHB read
2015-01-09 00:03:28 +05:30
ich.c
Merge branch 'master' of git://git.denx.de/u-boot-spi
2015-10-28 16:56:43 -04:00
ich.h
x86: spi: Support ValleyView in ICH SPI driver
2015-02-06 12:07:38 -07:00
Kconfig
spi: Kconfig: Add Zynq QSPI controller entry
2015-10-25 20:17:02 +05:30
kirkwood_spi.c
spi: kirkwood_spi.c: Change KW_SPI_BASE to MVEBU_SPI_BASE
2014-10-23 09:59:21 -04:00
lpc32xx_ssp.c
lpc32xx: add LPC32xx SSP support (SPI mode)
2015-04-10 14:23:20 +02:00
Makefile
spi: Add zynq qspi controller driver
2015-10-25 20:17:01 +05:30
mpc8xxx_spi.c
spi: mpc8xxx_spi: Use BIT macro
2015-10-27 23:21:28 +05:30
mpc52xx_spi.c
Add GPL-2.0+ SPDX-License-Identifier to source files
2013-07-24 09:44:38 -04:00
mxc_spi.c
linux/kernel.h: sync min, max, min3, max3 macros with Linux
2014-11-23 06:48:30 -05:00
mxs_spi.c
Move ALLOC_CACHE_ALIGN_BUFFER() to the new memalign.h header
2015-09-11 17:15:20 -04:00
omap3_spi.c
spi: omap3: Fix timeout handling
2015-04-27 21:08:42 +05:30
omap3_spi.h
spi: omap3_spi: Use GENMASK
2015-10-27 23:21:43 +05:30
rk_spi.c
rockchip: Add SPI driver
2015-09-02 21:28:24 -06:00
rk_spi.h
rockchip: Add SPI driver
2015-09-02 21:28:24 -06:00
sandbox_spi.c
dm: spi: Move the per-child data size to the uclass
2015-01-29 17:09:55 -07:00
sh_qspi.c
spi: sh_qspi: Use BIT macro
2015-10-27 23:21:28 +05:30
sh_spi.c
spi: sh_spi: Use sh_spi_clear_bit() instead of open-coded
2014-01-11 12:21:31 +05:30
sh_spi.h
sh_spi: Add 4 chip select signals supporting
2012-03-26 10:09:31 +09:00
soft_spi.c
dm: Rename dev_get_parentdata() to dev_get_parent_priv()
2015-10-23 09:42:28 -06:00
soft_spi_legacy.c
dm: spi: Remove SPI_INIT feature
2014-10-22 10:36:48 -06:00
spi-emul-uclass.c
dm: sandbox: Add a SPI emulation uclass
2014-10-22 10:36:46 -06:00
spi-uclass.c
dm: Rename dev_get_parentdata() to dev_get_parent_priv()
2015-10-23 09:42:28 -06:00
spi.c
spi: Support half-duplex mode in FDT decode
2014-08-06 00:18:01 +05:30
tegra20_sflash.c
spi: tegra: Use GENMASK
2015-10-27 23:21:43 +05:30
tegra20_slink.c
spi: tegra: Use GENMASK
2015-10-27 23:21:43 +05:30
tegra114_spi.c
spi: tegra: Use GENMASK
2015-10-27 23:21:43 +05:30
tegra_spi.h
dm: tegra: spi: Convert to driver model
2014-10-22 10:36:52 -06:00
ti_qspi.c
spi: ti_qspi: Use BIT macro
2015-10-27 23:21:33 +05:30
xilinx_spi.c
spi: xilinx_spi: Use GENMASK
2015-10-27 23:21:43 +05:30
zynq_qspi.c
spi: zynq_[q]spi: Use GENMASK macro
2015-10-27 23:19:15 +05:30
zynq_spi.c
spi: zynq_[q]spi: Use GENMASK macro
2015-10-27 23:19:15 +05:30