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3a21773129
SolidRun has designed the Hummingboard board based on mx6q/dl/solo. Add the initial support for the mx6 solo variant. More information about this hardware can be found at: http://imx.solid-run.com/wiki/index.php?title=Carrier-One_Hardware (Carrier-One was the previous name of Hummingboard). Based on the work from Jon Nettleton <jon.nettleton@gmail.com>. Signed-off-by: Jon Nettleton <jon.nettleton@gmail.com> Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
76 lines
2.5 KiB
INI
76 lines
2.5 KiB
INI
/*
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* Copyright (C) 2013 Boundary Devices
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* Copyright (C) 2013 SolidRun ltd.
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* Copyright (C) 2013 Jon Nettleton <jon.nettleton@gmail.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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/*
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* DDR3 settings
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* MX6Q ddr is limited to 1066 Mhz currently 1056 MHz(528 MHz clock),
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* memory bus width: 64 bits x16/x32/x64
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* MX6DL ddr is limited to 800 MHz(400 MHz clock)
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* memory bus width: 64 bits x16/x32/x64
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* MX6SOLO ddr is limited to 800 MHz(400 MHz clock)
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* memory bus width: 32 bits x16/x32
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*/
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/* DDR IO TYPE */
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DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000c0000
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DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000
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/* Clock */
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DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000028
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/* Address */
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DATA 4, MX6_IOM_DRAM_CAS, 0x00000010
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DATA 4, MX6_IOM_DRAM_RAS, 0x00000010
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DATA 4, MX6_IOM_GRP_ADDDS, 0x00000010
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/* Control */
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DATA 4, MX6_IOM_DRAM_RESET, 0x00000010
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DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000
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DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDODT0, 0x00000010
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DATA 4, MX6_IOM_DRAM_SDODT1, 0x00000010
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DATA 4, MX6_IOM_GRP_CTLDS, 0x00000010
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/*
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* Data Strobe: IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL - DDR_INPUT=0, CMOS,
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* CMOS mode saves power, but have less timing margin in case of DDR
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* timing issue on your board you can try DDR_MODE: [= 0x00020000]
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*/
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DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000
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DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000028
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DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000000
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DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000000
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/*
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* DATA:IOMUXC_SW_PAD_CTL_GRP_DDRMODE - DDR_INPUT=0, CMOS,
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* CMOS mode saves power, but have less timing margin in case of DDR
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* timing issue on your board you can try DDR_MODE: [= 0x00020000]
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*/
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DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000
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DATA 4, MX6_IOM_GRP_B0DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B1DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B2DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B3DS, 0x00000028
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DATA 4, MX6_IOM_GRP_B4DS, 0x00000000
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DATA 4, MX6_IOM_GRP_B5DS, 0x00000000
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DATA 4, MX6_IOM_GRP_B6DS, 0x00000000
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DATA 4, MX6_IOM_GRP_B7DS, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM0, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM1, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM2, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM3, 0x00000028
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DATA 4, MX6_IOM_DRAM_DQM4, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM5, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM6, 0x00000000
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DATA 4, MX6_IOM_DRAM_DQM7, 0x00000000
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