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https://github.com/AsahiLinux/u-boot
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77b11f7604
As part of the effort of making U-Boot work with the same device tree as Linux, there is an issue with the "xfi" phy-mode. To be precise, in Linux there was a discussion (for those who have time to read: https://lore.kernel.org/netdev/1576768881-24971-2-git-send-email-madalin.bucur@oss.nxp.com/) which led to a patch: https://git.kernel.org/pub/scm/linux/kernel/git/netdev/net-next.git/commit/?id=c114574ebfdf42f826776f717c8056a00fa94881 TL;DR: "xfi" was standardized in Linux as "10gbase-r". This patch changes the relevant occurrences in U-Boot to use "10gbase-r" instead of "xfi" wherever applicable. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> |
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cpld.c | ||
cpld.h | ||
ddr.c | ||
ddr.h | ||
eth.c | ||
Kconfig | ||
ls1043ardb.c | ||
ls1043ardb_pbi.cfg | ||
ls1043ardb_rcw_nand.cfg | ||
ls1043ardb_rcw_sd.cfg | ||
MAINTAINERS | ||
Makefile | ||
README |
Overview -------- The LS1043A Reference Design Board (RDB) is a high-performance computing, evaluation, and development platform that supports the QorIQ LS1043A LayerScape Architecture processor. The LS1043ARDB provides SW development platform for the Freescale LS1043A processor series, with a complete debugging environment. The LS1043A RDB is lead-free and RoHS-compliant. LS1043A SoC Overview -------------------- Please refer arch/arm/cpu/armv8/fsl-layerscape/doc/README.soc for LS1043A SoC overview. LS1043ARDB board Overview ----------------------- - SERDES Connections, 4 lanes supporting: - PCI Express 2.0 with two PCIe connectors supporting: miniPCIe card and standard PCIe card - QSGMII with x4 RJ45 connector - 10GBase-R with x1 RJ45 connector - DDR Controller - 2GB 32bits DDR4 SDRAM. Support rates of up to 1600MT/s -IFC/Local Bus - One 128MB NOR flash 16-bit data bus - One 512 MB NAND flash with ECC support - CPLD connection - USB 3.0 - Two super speed USB 3.0 Type A ports - SDHC: connects directly to a full SD/MMC slot - DSPI: 16 MB high-speed flash Memory for boot code and storage (up to 108MHz) - 4 I2C controllers - UART - Two 4-pin serial ports at up to 115.2 Kbit/s - Two DB9 D-Type connectors supporting one Serial port each - ARM JTAG support Memory map from core's view ---------------------------- Start Address End Address Description Size 0x00_0000_0000 0x00_000F_FFFF Secure Boot ROM 1MB 0x00_0100_0000 0x00_0FFF_FFFF CCSRBAR 240MB 0x00_1000_0000 0x00_1000_FFFF OCRAM0 64KB 0x00_1001_0000 0x00_1001_FFFF OCRAM1 64KB 0x00_2000_0000 0x00_20FF_FFFF DCSR 16MB 0x00_6000_0000 0x00_67FF_FFFF IFC - NOR Flash 128MB 0x00_7E80_0000 0x00_7E80_FFFF IFC - NAND Flash 64KB 0x00_7FB0_0000 0x00_7FB0_0FFF IFC - FPGA 4KB 0x00_8000_0000 0x00_FFFF_FFFF DRAM1 2GB Booting Options --------------- a) NOR boot b) NAND boot c) SD boot