mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-08 06:04:34 +00:00
35b65dd8ef
Historically, the reset_cpu() function had an `addr` parameter which was
meant to pass in an address of the reset vector location, where the CPU
should reset to. This feature is no longer used anywhere in U-Boot as
all reset_cpu() implementations now ignore the passed value. Generic
code has been added which always calls reset_cpu() with `0` which means
this feature can no longer be used easily anyway.
Over time, many implementations seem to have "misunderstood" the
existence of this parameter as a way to customize/parameterize the reset
(e.g. COLD vs WARM resets). As this is not properly supported, the
code will almost always not do what it is intended to (because all
call-sites just call reset_cpu() with 0).
To avoid confusion and to clean up the codebase from unused left-overs
of the past, remove the `addr` parameter entirely. Code which intends
to support different kinds of resets should be rewritten as a sysreset
driver instead.
This transformation was done with the following coccinelle patch:
@@
expression argvalue;
@@
- reset_cpu(argvalue)
+ reset_cpu()
@@
identifier argname;
type argtype;
@@
- reset_cpu(argtype argname)
+ reset_cpu(void)
{ ... }
Signed-off-by: Harald Seiler <hws@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
165 lines
3.3 KiB
C
165 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* (C) Copyright 2013
|
|
* David Feng <fenghua@phytium.com.cn>
|
|
* Sharma Bhupesh <bhupesh.sharma@freescale.com>
|
|
*/
|
|
#include <common.h>
|
|
#include <cpu_func.h>
|
|
#include <dm.h>
|
|
#include <init.h>
|
|
#include <malloc.h>
|
|
#include <errno.h>
|
|
#include <net.h>
|
|
#include <netdev.h>
|
|
#include <asm/global_data.h>
|
|
#include <asm/io.h>
|
|
#include <linux/compiler.h>
|
|
#include <dm/platform_data/serial_pl01x.h>
|
|
#include "pcie.h"
|
|
#include <asm/armv8/mmu.h>
|
|
|
|
DECLARE_GLOBAL_DATA_PTR;
|
|
|
|
static const struct pl01x_serial_plat serial_plat = {
|
|
.base = V2M_UART0,
|
|
.type = TYPE_PL011,
|
|
.clock = CONFIG_PL011_CLOCK,
|
|
};
|
|
|
|
U_BOOT_DRVINFO(vexpress_serials) = {
|
|
.name = "serial_pl01x",
|
|
.plat = &serial_plat,
|
|
};
|
|
|
|
static struct mm_region vexpress64_mem_map[] = {
|
|
{
|
|
.virt = 0x0UL,
|
|
.phys = 0x0UL,
|
|
.size = 0x80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
|
|
PTE_BLOCK_NON_SHARE |
|
|
PTE_BLOCK_PXN | PTE_BLOCK_UXN
|
|
}, {
|
|
.virt = 0x80000000UL,
|
|
.phys = 0x80000000UL,
|
|
.size = 0xff80000000UL,
|
|
.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
|
|
PTE_BLOCK_INNER_SHARE
|
|
}, {
|
|
/* List terminator */
|
|
0,
|
|
}
|
|
};
|
|
|
|
struct mm_region *mem_map = vexpress64_mem_map;
|
|
|
|
/* This function gets replaced by platforms supporting PCIe.
|
|
* The replacement function, eg. on Juno, initialises the PCIe bus.
|
|
*/
|
|
__weak void vexpress64_pcie_init(void)
|
|
{
|
|
}
|
|
|
|
int board_init(void)
|
|
{
|
|
vexpress64_pcie_init();
|
|
return 0;
|
|
}
|
|
|
|
int dram_init(void)
|
|
{
|
|
gd->ram_size = PHYS_SDRAM_1_SIZE;
|
|
return 0;
|
|
}
|
|
|
|
int dram_init_banksize(void)
|
|
{
|
|
gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
|
|
gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
|
|
#ifdef PHYS_SDRAM_2
|
|
gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
|
|
gd->bd->bi_dram[1].size = PHYS_SDRAM_2_SIZE;
|
|
#endif
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_OF_BOARD
|
|
#define JUNO_FLASH_SEC_SIZE (256 * 1024)
|
|
static phys_addr_t find_dtb_in_nor_flash(const char *partname)
|
|
{
|
|
phys_addr_t sector = CONFIG_SYS_FLASH_BASE;
|
|
int i;
|
|
|
|
for (i = 0;
|
|
i < CONFIG_SYS_MAX_FLASH_SECT;
|
|
i++, sector += JUNO_FLASH_SEC_SIZE) {
|
|
int len = strlen(partname) + 1;
|
|
int offs;
|
|
phys_addr_t imginfo;
|
|
u32 reg;
|
|
|
|
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x04);
|
|
/* This makes up the string "HSLFTOOF" flash footer */
|
|
if (reg != 0x464F4F54U)
|
|
continue;
|
|
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x08);
|
|
if (reg != 0x464C5348U)
|
|
continue;
|
|
|
|
for (offs = 0; offs < 32; offs += 4, len -= 4) {
|
|
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x30 + offs);
|
|
if (strncmp(partname + offs, (char *)®,
|
|
len > 4 ? 4 : len))
|
|
break;
|
|
|
|
if (len > 4)
|
|
continue;
|
|
|
|
reg = readl(sector + JUNO_FLASH_SEC_SIZE - 0x10);
|
|
imginfo = sector + JUNO_FLASH_SEC_SIZE - 0x30 - reg;
|
|
reg = readl(imginfo + 0x54);
|
|
|
|
return CONFIG_SYS_FLASH_BASE +
|
|
reg * JUNO_FLASH_SEC_SIZE;
|
|
}
|
|
}
|
|
|
|
printf("No DTB found\n");
|
|
|
|
return ~0;
|
|
}
|
|
|
|
void *board_fdt_blob_setup(void)
|
|
{
|
|
phys_addr_t fdt_rom_addr = find_dtb_in_nor_flash(CONFIG_JUNO_DTB_PART);
|
|
|
|
if (fdt_rom_addr == ~0UL)
|
|
return NULL;
|
|
|
|
return (void *)fdt_rom_addr;
|
|
}
|
|
#endif
|
|
|
|
/* Actual reset is done via PSCI. */
|
|
void reset_cpu(void)
|
|
{
|
|
}
|
|
|
|
/*
|
|
* Board specific ethernet initialization routine.
|
|
*/
|
|
int board_eth_init(struct bd_info *bis)
|
|
{
|
|
int rc = 0;
|
|
#ifndef CONFIG_DM_ETH
|
|
#ifdef CONFIG_SMC91111
|
|
rc = smc91111_initialize(0, CONFIG_SMC91111_BASE);
|
|
#endif
|
|
#ifdef CONFIG_SMC911X
|
|
rc = smc911x_initialize(0, CONFIG_SMC911X_BASE);
|
|
#endif
|
|
#endif
|
|
return rc;
|
|
}
|