mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-11-16 01:38:22 +00:00
52923c6db7
AndeStar RISC-V(V5) provide mcache_ctl register which can configure I/D cache as enabled or disabled. This CSR will be encapsulated by CONFIG_RISCV_NDS. If you want to configure cache on AndeStar V5 AE350 platform. YOu can enable [*] AndeStar V5 ISA support by make menuconfig. This approach also provide the expansion when the vender specific features are going to join in. Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com>
27 lines
526 B
C
27 lines
526 B
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2017 Andes Technology Corporation
|
|
* Rick Chen, Andes Technology Corporation <rick@andestech.com>
|
|
*/
|
|
|
|
/* CPU specific code */
|
|
#include <common.h>
|
|
#include <asm/cache.h>
|
|
|
|
/*
|
|
* cleanup_before_linux() is called just before we call linux
|
|
* it prepares the processor for linux
|
|
*
|
|
* we disable interrupt and caches.
|
|
*/
|
|
int cleanup_before_linux(void)
|
|
{
|
|
disable_interrupts();
|
|
|
|
/* turn off I/D-cache */
|
|
cache_flush();
|
|
icache_disable();
|
|
dcache_disable();
|
|
|
|
return 0;
|
|
}
|