u-boot/arch/riscv/cpu/ax25
Rick Chen 61ce84b2cf riscv: cache: use CCTL to flush d-cache
Use CCTL command to do d-cache write back
and invalidate instead of fence.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
2019-09-03 09:31:03 +08:00
..
cache.c riscv: cache: use CCTL to flush d-cache 2019-09-03 09:31:03 +08:00
cpu.c riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00
Kconfig riscv: ax25: add imply v5l2 cache controller 2019-09-03 09:31:03 +08:00
Makefile riscv: cache: Implement i/dcache [status, enable, disable] 2018-11-26 13:58:01 +08:00