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Ls1028a SoC is based on Layerscape Chassis Generation 3.2 architecture with features: 2 ARM v8 Cortex-A72 cores, CCI400, SEC, DDR3L/4, LCD, GPU, TSN ENETC, 2 USB 3.0, 2 eSDHC, 2 FlexCAN, 2 SPI, SATA, 8 I2C controllers, 6 LPUARTs, GPIO, SAI, qDMA, eDMA, GIC, TMU etc. Signed-off-by: Sudhanshu Gupta <sudhanshu.gupta@nxp.com> Signed-off-by: Rai Harninder <harninder.rai@nxp.com> Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Signed-off-by: Bhaskar Upadhaya <Bhaskar.Upadhaya@nxp.com> Signed-off-by: Tang Yuantian <andy.tang@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> |
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.. | ||
clock.h | ||
config.h | ||
cpu.h | ||
fdt.h | ||
fsl_icid.h | ||
fsl_portals.h | ||
fsl_serdes.h | ||
immap_lsch2.h | ||
immap_lsch3.h | ||
imx-regs.h | ||
mmu.h | ||
mp.h | ||
ns_access.h | ||
ppa.h | ||
soc.h | ||
speed.h | ||
stream_id_lsch2.h | ||
stream_id_lsch3.h |