mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-09-30 03:12:07 +00:00
a2ac2b964b
This converts the following to Kconfig: CONFIG_SKIP_LOWLEVEL_INIT CONFIG_SKIP_LOWLEVEL_INIT_ONLY In order to do this, we need to introduce SPL and TPL variants of these options so that we can clearly disable these options only in SPL in some cases, and both instances in other cases. Signed-off-by: Tom Rini <trini@konsulko.com>
112 lines
2.3 KiB
ArmAsm
112 lines
2.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0+ */
|
|
/*
|
|
* armboot - Startup Code for ARM920 CPU-core
|
|
*
|
|
* Copyright (c) 2001 Marius Gröger <mag@sysgo.de>
|
|
* Copyright (c) 2002 Alex Züpke <azu@sysgo.de>
|
|
* Copyright (c) 2002 Gary Jennejohn <garyj@denx.de>
|
|
*/
|
|
|
|
#include <asm-offsets.h>
|
|
#include <common.h>
|
|
#include <config.h>
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* Startup Code (called from the ARM reset exception vector)
|
|
*
|
|
* do important init only if we don't start from memory!
|
|
* relocate armboot to ram
|
|
* setup stack
|
|
* jump to second stage
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
|
|
.globl reset
|
|
|
|
reset:
|
|
/*
|
|
* set the cpu to SVC32 mode
|
|
*/
|
|
mrs r0, cpsr
|
|
bic r0, r0, #0x1f
|
|
orr r0, r0, #0xd3
|
|
msr cpsr, r0
|
|
|
|
#if defined(CONFIG_AT91RM9200DK)
|
|
/*
|
|
* relocate exception table
|
|
*/
|
|
ldr r0, =_start
|
|
ldr r1, =0x0
|
|
mov r2, #16
|
|
copyex:
|
|
subs r2, r2, #1
|
|
ldr r3, [r0], #4
|
|
str r3, [r1], #4
|
|
bne copyex
|
|
#endif
|
|
|
|
/*
|
|
* we do sys-critical inits only at reboot,
|
|
* not when booting from ram!
|
|
*/
|
|
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
|
bl cpu_init_crit
|
|
#endif
|
|
|
|
bl _main
|
|
|
|
/*------------------------------------------------------------------------------*/
|
|
|
|
.globl c_runtime_cpu_setup
|
|
c_runtime_cpu_setup:
|
|
|
|
mov pc, lr
|
|
|
|
/*
|
|
*************************************************************************
|
|
*
|
|
* CPU_init_critical registers
|
|
*
|
|
* setup important registers
|
|
* setup memory timing
|
|
*
|
|
*************************************************************************
|
|
*/
|
|
|
|
|
|
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
|
|
cpu_init_crit:
|
|
/*
|
|
* flush v4 I/D caches
|
|
*/
|
|
mov r0, #0
|
|
mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */
|
|
mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */
|
|
|
|
/*
|
|
* disable MMU stuff and caches
|
|
*/
|
|
mrc p15, 0, r0, c1, c0, 0
|
|
bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS)
|
|
bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM)
|
|
orr r0, r0, #0x00000002 @ set bit 1 (A) Align
|
|
orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache
|
|
mcr p15, 0, r0, c1, c0, 0
|
|
|
|
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT_ONLY)
|
|
/*
|
|
* before relocating, we have to setup RAM timing
|
|
* because memory timing is board-dependend, you will
|
|
* find a lowlevel_init.S in your board directory.
|
|
*/
|
|
mov ip, lr
|
|
|
|
bl lowlevel_init
|
|
mov lr, ip
|
|
#endif
|
|
mov pc, lr
|
|
#endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */
|