u-boot/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
Hou Zhiqiang 0ea3671d35 armv8/fsl-lsch2: Implement workaround for PIN MUX erratum A010539
Pin mux logic has 2 options in priority order, one is through RCW_SRC
and then through RCW_Fields. In case of QSPI booting, RCW_SRC logic
takes the priority for SPI pads and do not allow RCW_BASE and SPI_EXT
to control the SPI muxing. But actually those are DSPI controller's
pads instead of QSPI controller's, so this workaround allows RCW
fields SPI_BASE and SPI_EXT to control relevant pads muxing.

Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[York Sun: Reformatted commit message]
Reviewed-by: York Sun <york.sun@nxp.com>
2016-10-06 09:57:36 -07:00

22 lines
554 B
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config ARCH_LS1012A
bool "Freescale Layerscape LS1012A SoC"
select SYS_FSL_MMDC
select SYS_FSL_ERRATUM_A010315
config ARCH_LS1043A
bool "Freescale Layerscape LS1043A SoC"
select SYS_FSL_ERRATUM_A010315
select SYS_FSL_ERRATUM_A010539
config ARCH_LS1046A
bool "Freescale Layerscape LS1046A SoC"
select SYS_FSL_ERRATUM_A010539
config SYS_FSL_MMDC
bool "Freescale Multi Mode DDR Controller"
config SYS_FSL_ERRATUM_A010315
bool "Workaround for PCIe erratum A010315"
config SYS_FSL_ERRATUM_A010539
bool "Workaround for PIN MUX erratum A010539"