mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-04 10:30:32 +00:00
6c4b50e6de
Change the PLL clock source from syscrg to sys_syscon child node. Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com> Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Reviewed-by: Torsten Duwe <duwe@suse.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
98 lines
1.4 KiB
Text
98 lines
1.4 KiB
Text
// SPDX-License-Identifier: GPL-2.0 OR MIT
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/*
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* Copyright (C) 2022 StarFive Technology Co., Ltd.
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*/
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#include <dt-bindings/reset/starfive,jh7110-crg.h>
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/ {
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cpus: cpus {
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bootph-pre-ram;
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S7_0: cpu@0 {
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bootph-pre-ram;
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status = "okay";
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cpu0_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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U74_1: cpu@1 {
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bootph-pre-ram;
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cpu1_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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U74_2: cpu@2 {
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bootph-pre-ram;
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cpu2_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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U74_3: cpu@3 {
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bootph-pre-ram;
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cpu3_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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U74_4: cpu@4 {
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bootph-pre-ram;
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cpu4_intc: interrupt-controller {
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bootph-pre-ram;
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};
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};
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};
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soc {
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bootph-pre-ram;
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clint: timer@2000000 {
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bootph-pre-ram;
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};
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dmc: dmc@15700000 {
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bootph-pre-ram;
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compatible = "starfive,jh7110-dmc";
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reg = <0x0 0x15700000 0x0 0x10000>,
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<0x0 0x13000000 0x0 0x10000>;
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resets = <&syscrg JH7110_SYSRST_DDR_AXI>,
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<&syscrg JH7110_SYSRST_DDR_OSC>,
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<&syscrg JH7110_SYSRST_DDR_APB>;
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reset-names = "axi", "osc", "apb";
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clocks = <&syscrg JH7110_SYSCLK_PLL1_OUT>;
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clock-names = "pll1_out";
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clock-frequency = <2133>;
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};
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};
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};
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&osc {
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bootph-pre-ram;
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};
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&gmac0_rmii_refin {
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bootph-pre-ram;
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};
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&aoncrg {
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bootph-pre-ram;
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};
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&syscrg {
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bootph-pre-ram;
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};
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&stgcrg {
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bootph-pre-ram;
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};
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&sys_syscon {
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bootph-pre-ram;
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};
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&S7_0 {
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status = "okay";
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};
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