Yu Chien Peter Lin 8a0d5f2f51 riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode ... The Andes PLMT driver directly accesses the mtime MMIO region, indicating its intended use in the M-mode boot stage. However, since U-Boot proper (S-mode) also uses the PLMT driver, we need to specifically mark the region as readable through PMPCFGx (or S/U-mode read-only shared data region for Smepmp) in OpenSBI. Granting permission for this case doesn't make sense. Instead, we should use the generic RISC-V timer driver to read the mtime through the TIME CSR. Therefore, we add the SPL_ANDES_PLMT_TIMER config, which ensures that the PLMT driver is linked exclusively against M-mode U-Boot or U-Boot SPL binaries. Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com> Reviewed-by: Samuel Holland <samuel@sholland.org>		2023-10-04 18:23:54 +08:00
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cpu	riscv: andesv5: Prefer using the generic RISC-V timer driver in S-mode	2023-10-04 18:23:54 +08:00
dts	configs: andes: add vender prefix for target name	2023-10-04 18:00:51 +08:00
include/asm	Merge branch 'next'	2023-10-02 10:55:44 -04:00
lib	riscv: bootstage: correct bootstage_report guard	2023-10-04 17:55:17 +08:00
config.mk	riscv: Support CONFIG_REMAKE_ELF	2023-04-20 20:45:08 +08:00
Kconfig	configs: andes: add vender prefix for target name	2023-10-04 18:00:51 +08:00
Makefile	riscv: support building double-float modules	2022-10-20 15:22:21 +08:00