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https://github.com/AsahiLinux/u-boot
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04f3da3936
If the DRAM clock duty does not meet the allowable tolerance, it is marked in an efuse register. If the register is fused, the boot code should compensate for the DRAM clock duty error. Signed-off-by: Kotaro Hayashi <hayashi.kotaro@socionext.com> [masahiro: simplify code, add git-log] Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
636 lines
18 KiB
C
636 lines
18 KiB
C
/*
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* Copyright (C) 2016-2017 Socionext Inc.
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*
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* based on commit 5ffd75ecd4929f22361ef65a35f0331d2fbc0f35 of Diag
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <common.h>
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#include <linux/bitops.h>
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#include <linux/compat.h>
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#include <linux/errno.h>
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#include <linux/io.h>
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#include <linux/sizes.h>
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#include <asm/processor.h>
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#include "../init.h"
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#include "ddruqphy-regs.h"
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#include "umc64-regs.h"
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#define DRAM_CH_NR 3
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enum dram_freq {
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DRAM_FREQ_1866M,
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DRAM_FREQ_NR,
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};
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enum dram_size {
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DRAM_SZ_256M,
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DRAM_SZ_512M,
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DRAM_SZ_NR,
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};
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enum dram_board { /* board type */
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DRAM_BOARD_LD20_REF, /* LD20 reference */
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DRAM_BOARD_LD20_GLOBAL, /* LD20 TV */
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DRAM_BOARD_LD20_C1, /* LD20 TV C1 */
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DRAM_BOARD_LD21_REF, /* LD21 reference */
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DRAM_BOARD_LD21_GLOBAL, /* LD21 TV */
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DRAM_BOARD_NR,
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};
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/* PHY */
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static const int ddrphy_adrctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
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{268 - 262, 268 - 263, 268 - 378}, /* LD20 reference */
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{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV */
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{268 - 262, 268 - 263, 268 - 378}, /* LD20 TV C1 */
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{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 reference */
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{268 - 212, 268 - 268, /* No CH2 */}, /* LD21 TV */
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};
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static const int ddrphy_dlltrimclk[DRAM_BOARD_NR][DRAM_CH_NR] = {
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{268, 268, 268}, /* LD20 reference */
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{268, 268, 268}, /* LD20 TV */
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{189, 189, 189}, /* LD20 TV C1 */
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{268, 268 + 252, /* No CH2 */}, /* LD21 reference */
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{268, 268 + 202, /* No CH2 */}, /* LD21 TV */
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};
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static const int ddrphy_dllrecalib[DRAM_BOARD_NR][DRAM_CH_NR] = {
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{268 - 378, 268 - 263, 268 - 378}, /* LD20 reference */
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{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV */
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{268 - 378, 268 - 263, 268 - 378}, /* LD20 TV C1 */
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{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 reference */
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{268 - 212, 268 - 536, /* No CH2 */}, /* LD21 TV */
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};
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static const u32 ddrphy_phy_pad_ctrl[DRAM_BOARD_NR][DRAM_CH_NR] = {
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{0x50B840B1, 0x50B840B1, 0x50B840B1}, /* LD20 reference */
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{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV */
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{0x50BB40B1, 0x50BB40B1, 0x50BB40B1}, /* LD20 TV C1 */
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{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 reference */
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{0x50BB40B4, 0x50B840B1, /* No CH2 */}, /* LD21 TV */
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};
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static const u32 ddrphy_scl_gate_timing[DRAM_CH_NR] = {
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0x00000140, 0x00000180, 0x00000140
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};
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static const short ddrphy_op_dq_shift_val_ld20[DRAM_CH_NR][32] = {
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{
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2, 1, 0, 1, 2, 1, 1, 1,
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2, 1, 1, 2, 1, 1, 1, 1,
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1, 2, 1, 1, 1, 2, 1, 1,
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2, 2, 0, 1, 1, 2, 2, 1,
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},
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{
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1, 1, 0, 1, 2, 2, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 0, 0, 1, 1, 0, 0,
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0, 1, 1, 1, 2, 1, 2, 1,
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},
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{
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2, 2, 0, 2, 1, 1, 2, 1,
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1, 1, 0, 1, 1, -1, 1, 1,
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2, 2, 2, 2, 1, 1, 1, 1,
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1, 1, 1, 0, 2, 2, 1, 2,
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},
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};
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static const short ddrphy_op_dq_shift_val_ld21[DRAM_CH_NR][32] = {
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{
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1, 1, 0, 1, 1, 1, 1, 1,
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1, 0, 0, 0, 1, 1, 0, 2,
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1, 1, 0, 0, 1, 1, 1, 1,
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1, 0, 0, 0, 1, 0, 0, 1,
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},
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{ 1, 0, 2, 1, 1, 1, 1, 0,
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1, 0, 0, 1, 0, 1, 0, 0,
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1, 0, 1, 0, 1, 1, 1, 0,
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1, 1, 1, 1, 0, 1, 0, 0,
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},
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/* No CH2 */
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};
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static const short (* const ddrphy_op_dq_shift_val[DRAM_BOARD_NR])[32] = {
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ddrphy_op_dq_shift_val_ld20, /* LD20 reference */
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ddrphy_op_dq_shift_val_ld20, /* LD20 TV */
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ddrphy_op_dq_shift_val_ld20, /* LD20 TV C */
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ddrphy_op_dq_shift_val_ld21, /* LD21 reference */
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ddrphy_op_dq_shift_val_ld21, /* LD21 TV */
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};
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static const short ddrphy_ip_dq_shift_val_ld20[DRAM_CH_NR][32] = {
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{
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3, 3, 3, 2, 3, 2, 0, 2,
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2, 3, 3, 1, 2, 2, 2, 2,
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2, 2, 2, 2, 0, 1, 1, 1,
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2, 2, 2, 2, 3, 0, 2, 2,
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},
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{
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2, 2, 1, 1, -1, 1, 1, 1,
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2, 0, 2, 2, 2, 1, 0, 2,
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2, 1, 2, 1, 0, 1, 1, 1,
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2, 2, 2, 2, 2, 2, 2, 2,
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},
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{
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2, 2, 3, 2, 1, 2, 2, 2,
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2, 3, 4, 2, 3, 4, 3, 3,
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2, 2, 1, 2, 1, 1, 1, 1,
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2, 2, 2, 2, 1, 2, 2, 1,
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},
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};
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static const short ddrphy_ip_dq_shift_val_ld21[DRAM_CH_NR][32] = {
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{
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2, 2, 2, 2, 1, 2, 2, 2,
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2, 3, 3, 2, 2, 2, 2, 2,
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2, 1, 2, 2, 1, 1, 1, 1,
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2, 2, 2, 3, 1, 2, 2, 2,
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},
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{
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3, 4, 4, 1, 0, 1, 1, 1,
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1, 2, 1, 2, 2, 3, 3, 2,
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1, 0, 2, 1, 1, 0, 1, 0,
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0, 1, 0, 0, 1, 1, 0, 1,
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},
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/* No CH2 */
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};
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static const short (* const ddrphy_ip_dq_shift_val[DRAM_BOARD_NR])[32] = {
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ddrphy_ip_dq_shift_val_ld20, /* LD20 reference */
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ddrphy_ip_dq_shift_val_ld20, /* LD20 TV */
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ddrphy_ip_dq_shift_val_ld20, /* LD20 TV C */
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ddrphy_ip_dq_shift_val_ld21, /* LD21 reference */
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ddrphy_ip_dq_shift_val_ld21, /* LD21 TV */
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};
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static void ddrphy_select_lane(void __iomem *phy_base, unsigned int lane,
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unsigned int bit)
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{
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WARN_ON(lane >= 1 << PHY_LANE_SEL_LANE_WIDTH);
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WARN_ON(bit >= 1 << PHY_LANE_SEL_BIT_WIDTH);
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writel((bit << PHY_LANE_SEL_BIT_SHIFT) |
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(lane << PHY_LANE_SEL_LANE_SHIFT),
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phy_base + PHY_LANE_SEL);
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}
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#define DDRPHY_EFUSEMON (void *)0x5f900118
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static void ddrphy_init(void __iomem *phy_base, enum dram_board board, int ch)
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{
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writel(0x0C001001, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
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while (!(readl(phy_base + PHY_UNIQUIFY_TSMC_IO_1) & BIT(1)))
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cpu_relax();
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if (readl(DDRPHY_EFUSEMON) & BIT(ch))
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writel(0x00000000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
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else
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writel(0x0C001000, phy_base + PHY_UNIQUIFY_TSMC_IO_1);
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writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_3);
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writel(0x00000000, phy_base + PHY_DLL_INCR_TRIM_1);
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ddrphy_select_lane(phy_base, 0, 0);
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writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
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writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
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ddrphy_select_lane(phy_base, 6, 0);
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writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
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writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
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ddrphy_select_lane(phy_base, 12, 0);
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writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
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writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
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ddrphy_select_lane(phy_base, 18, 0);
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writel(0x00000005, phy_base + PHY_DLL_TRIM_1);
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writel(0x0000000a, phy_base + PHY_DLL_TRIM_3);
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writel(0x00000001, phy_base + PHY_SCL_WINDOW_TRIM);
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writel(0x00000000, phy_base + PHY_UNQ_ANALOG_DLL_1);
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writel(ddrphy_phy_pad_ctrl[board][ch], phy_base + PHY_PAD_CTRL);
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writel(0x00000070, phy_base + PHY_VREF_TRAINING);
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writel(0x01000075, phy_base + PHY_SCL_CONFIG_1);
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writel(0x00000501, phy_base + PHY_SCL_CONFIG_2);
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writel(0x00000000, phy_base + PHY_SCL_CONFIG_3);
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writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
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writel(0x00000000, phy_base + PHY_SCL_CONFIG_4);
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writel(ddrphy_scl_gate_timing[ch], phy_base + PHY_SCL_GATE_TIMING);
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writel(0x02a000a0, phy_base + PHY_WRLVL_DYN_ODT);
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writel(0x00840004, phy_base + PHY_WRLVL_ON_OFF);
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writel(0x0000020d, phy_base + PHY_DLL_ADRCTRL);
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ddrphy_select_lane(phy_base, 0, 0);
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writel(0x0000008d, phy_base + PHY_DLL_TRIM_CLK);
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writel(0xa800100d, phy_base + PHY_DLL_RECALIB);
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writel(0x00005076, phy_base + PHY_SCL_LATENCY);
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}
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static int ddrphy_to_dly_step(void __iomem *phy_base, unsigned int freq,
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int delay)
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{
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int mdl;
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mdl = (readl(phy_base + PHY_DLL_ADRCTRL) & PHY_DLL_ADRCTRL_MDL_MASK) >>
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PHY_DLL_ADRCTRL_MDL_SHIFT;
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return DIV_ROUND_CLOSEST((long)freq * delay * mdl, 2 * 1000000L);
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}
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static void ddrphy_set_delay(void __iomem *phy_base, unsigned int reg,
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u32 mask, u32 incr, int dly_step)
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{
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u32 tmp;
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tmp = readl(phy_base + reg);
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tmp &= ~mask;
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tmp |= min_t(u32, abs(dly_step), mask);
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if (dly_step >= 0)
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tmp |= incr;
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else
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tmp &= ~incr;
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writel(tmp, phy_base + reg);
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}
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static void ddrphy_set_dll_recalib(void __iomem *phy_base, int dly_step)
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{
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ddrphy_set_delay(phy_base, PHY_DLL_RECALIB,
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PHY_DLL_RECALIB_TRIM_MASK, PHY_DLL_RECALIB_INCR,
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dly_step);
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}
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static void ddrphy_set_dll_adrctrl(void __iomem *phy_base, int dly_step)
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{
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ddrphy_set_delay(phy_base, PHY_DLL_ADRCTRL,
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PHY_DLL_ADRCTRL_TRIM_MASK, PHY_DLL_ADRCTRL_INCR,
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dly_step);
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}
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static void ddrphy_set_dll_trim_clk(void __iomem *phy_base, int dly_step)
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{
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ddrphy_select_lane(phy_base, 0, 0);
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ddrphy_set_delay(phy_base, PHY_DLL_TRIM_CLK,
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PHY_DLL_TRIM_CLK_MASK, PHY_DLL_TRIM_CLK_INCR,
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dly_step);
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}
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static void ddrphy_init_tail(void __iomem *phy_base, enum dram_board board,
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unsigned int freq, int ch)
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{
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int step;
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step = ddrphy_to_dly_step(phy_base, freq, ddrphy_adrctrl[board][ch]);
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ddrphy_set_dll_adrctrl(phy_base, step);
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step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dlltrimclk[board][ch]);
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ddrphy_set_dll_trim_clk(phy_base, step);
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step = ddrphy_to_dly_step(phy_base, freq, ddrphy_dllrecalib[board][ch]);
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ddrphy_set_dll_recalib(phy_base, step);
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}
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static void ddrphy_shift_one_dq(void __iomem *phy_base, unsigned int reg,
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u32 mask, u32 incr, short shift_val)
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{
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u32 tmp;
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int val;
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tmp = readl(phy_base + reg);
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val = tmp & mask;
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if (!(tmp & incr))
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val = -val;
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val += shift_val;
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tmp &= ~(incr | mask);
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tmp |= min_t(u32, abs(val), mask);
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if (val >= 0)
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tmp |= incr;
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writel(tmp, phy_base + reg);
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}
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static void ddrphy_shift_dq(void __iomem *phy_base, unsigned int reg,
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u32 mask, u32 incr, u32 override,
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const short *shift_val_array)
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{
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u32 tmp;
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int dx, bit;
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tmp = readl(phy_base + reg);
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tmp |= override;
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writel(tmp, phy_base + reg);
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for (dx = 0; dx < 4; dx++) {
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for (bit = 0; bit < 8; bit++) {
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ddrphy_select_lane(phy_base,
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(PHY_BITLVL_DLY_WIDTH + 1) * dx,
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bit);
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ddrphy_shift_one_dq(phy_base, reg, mask, incr,
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shift_val_array[dx * 8 + bit]);
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}
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}
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ddrphy_select_lane(phy_base, 0, 0);
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}
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static int ddrphy_training(void __iomem *phy_base, enum dram_board board,
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int ch)
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{
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writel(0x0000000f, phy_base + PHY_WRLVL_AUTOINC_TRIM);
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writel(0x00010000, phy_base + PHY_DLL_TRIM_2);
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writel(0x50000000, phy_base + PHY_SCL_START);
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while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
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cpu_relax();
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writel(0x00000000, phy_base + PHY_DISABLE_GATING_FOR_SCL);
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writel(0xff00ff00, phy_base + PHY_SCL_DATA_0);
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writel(0xff00ff00, phy_base + PHY_SCL_DATA_1);
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writel(0xFBF8FFFF, phy_base + PHY_SCL_START_ADDR);
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writel(0x11000000, phy_base + PHY_SCL_START);
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while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
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cpu_relax();
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writel(0xFBF0FFFF, phy_base + PHY_SCL_START_ADDR);
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writel(0x30500000, phy_base + PHY_SCL_START);
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while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
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cpu_relax();
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writel(0x00000001, phy_base + PHY_DISABLE_GATING_FOR_SCL);
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writel(0x00000010, phy_base + PHY_SCL_MAIN_CLK_DELTA);
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writel(0x789b3de0, phy_base + PHY_SCL_DATA_0);
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writel(0xf10e4a56, phy_base + PHY_SCL_DATA_1);
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writel(0x11000000, phy_base + PHY_SCL_START);
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while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
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cpu_relax();
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writel(0x34000000, phy_base + PHY_SCL_START);
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while (readl(phy_base + PHY_SCL_START) & PHY_SCL_START_GO_DONE)
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cpu_relax();
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writel(0x00000003, phy_base + PHY_DISABLE_GATING_FOR_SCL);
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writel(0x000261c0, phy_base + PHY_DYNAMIC_WRITE_BIT_LVL);
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writel(0x00003270, phy_base + PHY_DYNAMIC_BIT_LVL);
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writel(0x011BD0C4, phy_base + PHY_DSCL_CNT);
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/* shift ip_dq trim */
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ddrphy_shift_dq(phy_base,
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PHY_IP_DQ_DQS_BITWISE_TRIM,
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PHY_IP_DQ_DQS_BITWISE_TRIM_MASK,
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PHY_IP_DQ_DQS_BITWISE_TRIM_INC,
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PHY_IP_DQ_DQS_BITWISE_TRIM_OVERRIDE,
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ddrphy_ip_dq_shift_val[board][ch]);
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/* shift op_dq trim */
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ddrphy_shift_dq(phy_base,
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PHY_OP_DQ_DM_DQS_BITWISE_TRIM,
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PHY_OP_DQ_DM_DQS_BITWISE_TRIM_MASK,
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PHY_OP_DQ_DM_DQS_BITWISE_TRIM_INC,
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PHY_OP_DQ_DM_DQS_BITWISE_TRIM_OVERRIDE,
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ddrphy_op_dq_shift_val[board][ch]);
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return 0;
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}
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/* UMC */
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static const u32 umc_initctla[DRAM_FREQ_NR] = {0x71016D11};
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static const u32 umc_initctlb[DRAM_FREQ_NR] = {0x07E390AC};
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static const u32 umc_initctlc[DRAM_FREQ_NR] = {0x00FF00FF};
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|
static const u32 umc_drmmr0[DRAM_FREQ_NR] = {0x00000114};
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|
static const u32 umc_drmmr2[DRAM_FREQ_NR] = {0x000002a0};
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|
|
|
static const u32 umc_memconf0a[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
|
/* 256MB 512MB */
|
|
{0x00000601, 0x00000801}, /* 1866 MHz */
|
|
};
|
|
|
|
static const u32 umc_memconf0b[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
|
/* 256MB 512MB */
|
|
{0x00000120, 0x00000130}, /* 1866 MHz */
|
|
};
|
|
|
|
static const u32 umc_memconfch[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
|
/* 256MB 512MB */
|
|
{0x00033603, 0x00033803}, /* 1866 MHz */
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|
};
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|
|
|
static const u32 umc_cmdctla[DRAM_FREQ_NR] = {0x060D0D20};
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|
static const u32 umc_cmdctlb[DRAM_FREQ_NR] = {0x2D211C08};
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|
static const u32 umc_cmdctlc[DRAM_FREQ_NR] = {0x00150C04};
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|
static const u32 umc_cmdctle[DRAM_FREQ_NR][DRAM_SZ_NR] = {
|
|
/* 256MB 512MB */
|
|
{0x0049071D, 0x0078071D}, /* 1866 MHz */
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|
};
|
|
|
|
static const u32 umc_rdatactl[DRAM_FREQ_NR] = {0x00000610};
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|
static const u32 umc_wdatactl[DRAM_FREQ_NR] = {0x00000204};
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|
static const u32 umc_odtctl[DRAM_FREQ_NR] = {0x02000002};
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|
static const u32 umc_dataset[DRAM_FREQ_NR] = {0x04000000};
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|
|
|
static const u32 umc_flowctla[DRAM_FREQ_NR] = {0x0081E01E};
|
|
static const u32 umc_directbusctrla[DRAM_CH_NR] = {
|
|
0x00000000, 0x00000001, 0x00000001
|
|
};
|
|
|
|
static void umc_poll_phy_init_complete(void __iomem *dc_base)
|
|
{
|
|
/* Wait for PHY Init Complete */
|
|
while (!(readl(dc_base + UMC_DFISTCTLC) & BIT(0)))
|
|
cpu_relax();
|
|
}
|
|
|
|
static int umc_dc_init(void __iomem *dc_base, unsigned int freq,
|
|
unsigned long size, int ch)
|
|
{
|
|
enum dram_freq freq_e;
|
|
enum dram_size size_e;
|
|
|
|
switch (freq) {
|
|
case 1866:
|
|
freq_e = DRAM_FREQ_1866M;
|
|
break;
|
|
default:
|
|
pr_err("unsupported DRAM frequency %ud MHz\n", freq);
|
|
return -EINVAL;
|
|
}
|
|
|
|
switch (size) {
|
|
case 0:
|
|
return 0;
|
|
case SZ_256M:
|
|
size_e = DRAM_SZ_256M;
|
|
break;
|
|
case SZ_512M:
|
|
size_e = DRAM_SZ_512M;
|
|
break;
|
|
default:
|
|
pr_err("unsupported DRAM size 0x%08lx (per 16bit) for ch%d\n",
|
|
size, ch);
|
|
return -EINVAL;
|
|
}
|
|
|
|
writel(0x00000001, dc_base + UMC_DFICSOVRRD);
|
|
writel(0x00000000, dc_base + UMC_DFITURNOFF);
|
|
|
|
writel(umc_initctla[freq_e], dc_base + UMC_INITCTLA);
|
|
writel(umc_initctlb[freq_e], dc_base + UMC_INITCTLB);
|
|
writel(umc_initctlc[freq_e], dc_base + UMC_INITCTLC);
|
|
|
|
writel(umc_drmmr0[freq_e], dc_base + UMC_DRMMR0);
|
|
writel(0x00000004, dc_base + UMC_DRMMR1);
|
|
writel(umc_drmmr2[freq_e], dc_base + UMC_DRMMR2);
|
|
writel(0x00000000, dc_base + UMC_DRMMR3);
|
|
|
|
writel(umc_memconf0a[freq_e][size_e], dc_base + UMC_MEMCONF0A);
|
|
writel(umc_memconf0b[freq_e][size_e], dc_base + UMC_MEMCONF0B);
|
|
writel(umc_memconfch[freq_e][size_e], dc_base + UMC_MEMCONFCH);
|
|
writel(0x00000000, dc_base + UMC_MEMMAPSET);
|
|
|
|
writel(umc_cmdctla[freq_e], dc_base + UMC_CMDCTLA);
|
|
writel(umc_cmdctlb[freq_e], dc_base + UMC_CMDCTLB);
|
|
writel(umc_cmdctlc[freq_e], dc_base + UMC_CMDCTLC);
|
|
writel(umc_cmdctle[freq_e][size_e], dc_base + UMC_CMDCTLE);
|
|
|
|
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D0);
|
|
writel(umc_rdatactl[freq_e], dc_base + UMC_RDATACTL_D1);
|
|
|
|
writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D0);
|
|
writel(umc_wdatactl[freq_e], dc_base + UMC_WDATACTL_D1);
|
|
writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D0);
|
|
writel(umc_odtctl[freq_e], dc_base + UMC_ODTCTL_D1);
|
|
writel(umc_dataset[freq_e], dc_base + UMC_DATASET);
|
|
|
|
writel(0x00400020, dc_base + UMC_DCCGCTL);
|
|
writel(0x00000003, dc_base + UMC_ACSSETA);
|
|
writel(0x00000103, dc_base + UMC_FLOWCTLG);
|
|
writel(0x00010200, dc_base + UMC_ACSSETB);
|
|
|
|
writel(umc_flowctla[freq_e], dc_base + UMC_FLOWCTLA);
|
|
writel(0x00004444, dc_base + UMC_FLOWCTLC);
|
|
writel(0x00000000, dc_base + UMC_DFICUPDCTLA);
|
|
|
|
writel(0x00202000, dc_base + UMC_FLOWCTLB);
|
|
writel(0x00000000, dc_base + UMC_BSICMAPSET);
|
|
writel(0x00000000, dc_base + UMC_ERRMASKA);
|
|
writel(0x00000000, dc_base + UMC_ERRMASKB);
|
|
|
|
writel(umc_directbusctrla[ch], dc_base + UMC_DIRECTBUSCTRLA);
|
|
|
|
writel(0x00000001, dc_base + UMC_INITSET);
|
|
/* Wait for PHY Init Complete */
|
|
while (readl(dc_base + UMC_INITSTAT) & BIT(0))
|
|
cpu_relax();
|
|
|
|
writel(0x2A0A0A00, dc_base + UMC_SPCSETB);
|
|
writel(0x00000000, dc_base + UMC_DFICSOVRRD);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int umc_ch_init(void __iomem *umc_ch_base, void __iomem *phy_ch_base,
|
|
enum dram_board board, unsigned int freq,
|
|
unsigned long size, int ch)
|
|
{
|
|
void __iomem *dc_base = umc_ch_base + 0x00011000;
|
|
void __iomem *phy_base = phy_ch_base;
|
|
int ret;
|
|
|
|
/* PHY Update Mode (ON) */
|
|
writel(0x8000003f, dc_base + UMC_DFIPUPDCTLA);
|
|
|
|
/* deassert PHY reset signals */
|
|
writel(UMC_DIOCTLA_CTL_NRST | UMC_DIOCTLA_CFG_NRST,
|
|
dc_base + UMC_DIOCTLA);
|
|
|
|
ddrphy_init(phy_base, board, ch);
|
|
|
|
umc_poll_phy_init_complete(dc_base);
|
|
|
|
ddrphy_init_tail(phy_base, board, freq, ch);
|
|
|
|
ret = umc_dc_init(dc_base, freq, size, ch);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = ddrphy_training(phy_base, board, ch);
|
|
if (ret)
|
|
return ret;
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void um_init(void __iomem *um_base)
|
|
{
|
|
writel(0x000000ff, um_base + UMC_MBUS0);
|
|
writel(0x000000ff, um_base + UMC_MBUS1);
|
|
writel(0x000000ff, um_base + UMC_MBUS2);
|
|
writel(0x00000001, um_base + UMC_MBUS3);
|
|
writel(0x00000001, um_base + UMC_MBUS4);
|
|
writel(0x00000001, um_base + UMC_MBUS5);
|
|
writel(0x00000001, um_base + UMC_MBUS6);
|
|
writel(0x00000001, um_base + UMC_MBUS7);
|
|
writel(0x00000001, um_base + UMC_MBUS8);
|
|
writel(0x00000001, um_base + UMC_MBUS9);
|
|
writel(0x00000001, um_base + UMC_MBUS10);
|
|
}
|
|
|
|
int uniphier_ld20_umc_init(const struct uniphier_board_data *bd)
|
|
{
|
|
void __iomem *um_base = (void __iomem *)0x5b600000;
|
|
void __iomem *umc_ch_base = (void __iomem *)0x5b800000;
|
|
void __iomem *phy_ch_base = (void __iomem *)0x6e200000;
|
|
enum dram_board board;
|
|
int ch, ret;
|
|
|
|
switch (UNIPHIER_BD_BOARD_GET_TYPE(bd->flags)) {
|
|
case UNIPHIER_BD_BOARD_LD20_REF:
|
|
board = DRAM_BOARD_LD20_REF;
|
|
break;
|
|
case UNIPHIER_BD_BOARD_LD20_GLOBAL:
|
|
board = DRAM_BOARD_LD20_GLOBAL;
|
|
break;
|
|
case UNIPHIER_BD_BOARD_LD20_C1:
|
|
board = DRAM_BOARD_LD20_C1;
|
|
break;
|
|
case UNIPHIER_BD_BOARD_LD21_REF:
|
|
board = DRAM_BOARD_LD21_REF;
|
|
break;
|
|
case UNIPHIER_BD_BOARD_LD21_GLOBAL:
|
|
board = DRAM_BOARD_LD21_GLOBAL;
|
|
break;
|
|
default:
|
|
pr_err("unsupported board type %d\n",
|
|
UNIPHIER_BD_BOARD_GET_TYPE(bd->flags));
|
|
return -EINVAL;
|
|
}
|
|
|
|
for (ch = 0; ch < DRAM_CH_NR; ch++) {
|
|
unsigned long size = bd->dram_ch[ch].size;
|
|
unsigned int width = bd->dram_ch[ch].width;
|
|
|
|
if (size) {
|
|
ret = umc_ch_init(umc_ch_base, phy_ch_base, board,
|
|
bd->dram_freq, size / (width / 16),
|
|
ch);
|
|
if (ret) {
|
|
pr_err("failed to initialize UMC ch%d\n", ch);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
umc_ch_base += 0x00200000;
|
|
phy_ch_base += 0x00004000;
|
|
}
|
|
|
|
um_init(um_base);
|
|
|
|
return 0;
|
|
}
|