mirror of
https://github.com/AsahiLinux/u-boot
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56009451d8
This commit adds support for HDMI output. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
124 lines
2.4 KiB
C
124 lines
2.4 KiB
C
/*
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* Sunxi platform display controller register and constant defines
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*
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* (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
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*
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* Based on out of tree Linux DRM driver defines:
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* Copyright (C) 2016 Jean-Francois Moine <moinejf@free.fr>
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* Copyright (c) 2016 Allwinnertech Co., Ltd.
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#ifndef _SUNXI_DISPLAY2_H
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#define _SUNXI_DISPLAY2_H
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/* internal clock settings */
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struct de_clk {
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u32 gate_cfg;
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u32 bus_cfg;
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u32 rst_cfg;
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u32 div_cfg;
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u32 sel_cfg;
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};
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/* global control */
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struct de_glb {
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u32 ctl;
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u32 status;
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u32 dbuff;
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u32 size;
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};
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/* alpha blending */
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struct de_bld {
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u32 fcolor_ctl;
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struct {
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u32 fcolor;
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u32 insize;
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u32 offset;
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u32 dum;
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} attr[4];
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u32 dum0[15];
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u32 route;
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u32 premultiply;
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u32 bkcolor;
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u32 output_size;
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u32 bld_mode[4];
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u32 dum1[4];
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u32 ck_ctl;
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u32 ck_cfg;
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u32 dum2[2];
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u32 ck_max[4];
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u32 dum3[4];
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u32 ck_min[4];
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u32 dum4[3];
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u32 out_ctl;
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};
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/* VI channel */
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struct de_vi {
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struct {
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u32 attr;
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u32 size;
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u32 coord;
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u32 pitch[3];
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u32 top_laddr[3];
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u32 bot_laddr[3];
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} cfg[4];
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u32 fcolor[4];
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u32 top_haddr[3];
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u32 bot_haddr[3];
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u32 ovl_size[2];
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u32 hori[2];
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u32 vert[2];
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};
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struct de_ui {
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struct {
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u32 attr;
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u32 size;
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u32 coord;
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u32 pitch;
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u32 top_laddr;
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u32 bot_laddr;
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u32 fcolor;
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u32 dum;
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} cfg[4];
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u32 top_haddr;
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u32 bot_haddr;
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u32 ovl_size;
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};
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/*
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* DE register constants.
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*/
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#define SUNXI_DE2_MUX0_BASE (SUNXI_DE2_BASE + 0x100000)
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#define SUNXI_DE2_MUX1_BASE (SUNXI_DE2_BASE + 0x200000)
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#define SUNXI_DE2_MUX_GLB_REGS 0x00000
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#define SUNXI_DE2_MUX_BLD_REGS 0x01000
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#define SUNXI_DE2_MUX_CHAN_REGS 0x02000
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#define SUNXI_DE2_MUX_CHAN_SZ 0x1000
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#define SUNXI_DE2_MUX_VSU_REGS 0x20000
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#define SUNXI_DE2_MUX_GSU1_REGS 0x30000
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#define SUNXI_DE2_MUX_GSU2_REGS 0x40000
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#define SUNXI_DE2_MUX_GSU3_REGS 0x50000
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#define SUNXI_DE2_MUX_FCE_REGS 0xa0000
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#define SUNXI_DE2_MUX_BWS_REGS 0xa2000
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#define SUNXI_DE2_MUX_LTI_REGS 0xa4000
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#define SUNXI_DE2_MUX_PEAK_REGS 0xa6000
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#define SUNXI_DE2_MUX_ASE_REGS 0xa8000
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#define SUNXI_DE2_MUX_FCC_REGS 0xaa000
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#define SUNXI_DE2_MUX_DCSC_REGS 0xb0000
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#define SUNXI_DE2_FORMAT_XRGB_8888 4
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#define SUNXI_DE2_FORMAT_RGB_565 10
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#define SUNXI_DE2_MUX_GLB_CTL_EN (1 << 0)
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#define SUNXI_DE2_UI_CFG_ATTR_EN (1 << 0)
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#define SUNXI_DE2_UI_CFG_ATTR_FMT(f) ((f & 0xf) << 8)
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#define SUNXI_DE2_WH(w, h) (((h - 1) << 16) | (w - 1))
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#endif /* _SUNXI_DISPLAY2_H */
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