mirror of
https://github.com/AsahiLinux/u-boot
synced 2024-12-03 01:50:25 +00:00
44fb0d6c9f
FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file -----BEGIN PGP SIGNATURE----- iF0EABECAB0WIQQbPNTMvXmYlBPRwx7KSWXLKUoMIQUCXZ2mcwAKCRDKSWXLKUoM IT/KAJ4tL49YwINqCVGd7gafWvdfC4htygCcCgr9gLnJ+LjDQkxWT/r6faIcL00= =OnMk -----END PGP SIGNATURE----- Merge tag 'xilinx-for-v2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx/FPGA changes for v2020.01 FPGA: - Enable fpga loading on Versal - Minor fix Microblaze: - Fix LMB configurations to support initrds - Some other cleanups Zynq: - Minor config/dt changes - Add distro boot support for usb1 and mmc1 - Remove Xilinx private boot commands and use only distro boot ZynqMP: - Kconfig cleanups, defconfig updates - Update some dt files - Add firmware driver for talking to PMUFW - Extend distro boot support for jtag - Add new IDs - Add system controller configurations - Convert code to talk firmware via mailbox or SMCs Versal: - Add board_late_init() - Add run time DT memory setup - Add DFU support - Extend distro boot support for jtag and dfu - Add clock driver - Tune mini configurations Xilinx: - Improve documentation (boot scripts, dt binding) - Enable run time initrd_high calculation - Define default SYS_PROMPT - Add zynq/zynqmp virtual defconfig Drivers: - Add Xilinx mailbox driver for talking to firmware - Clean zynq_gem for Versal - Move ZYNQ_HISPD_BROKEN to Kconfig - Wire genphy_init() in phy.c - Add Xilinx gii2rgmii bridge - Cleanup zynq_sdhci - dwc3 fix - zynq_gpio fix - axi_emac fix Others: - apalis-tk1 - clean config file |
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| .. | ||
| altera | ||
| analogbits | ||
| aspeed | ||
| at91 | ||
| exynos | ||
| imx | ||
| mediatek | ||
| meson | ||
| mvebu | ||
| owl | ||
| renesas | ||
| rockchip | ||
| sifive | ||
| sunxi | ||
| tegra | ||
| uniphier | ||
| clk-composite.c | ||
| clk-divider.c | ||
| clk-fixed-factor.c | ||
| clk-gate.c | ||
| clk-hsdk-cgu.c | ||
| clk-mux.c | ||
| clk-ti-sci.c | ||
| clk-uclass.c | ||
| clk.c | ||
| clk_bcm6345.c | ||
| clk_boston.c | ||
| clk_fixed_factor.c | ||
| clk_fixed_rate.c | ||
| clk_pic32.c | ||
| clk_sandbox.c | ||
| clk_sandbox_ccf.c | ||
| clk_sandbox_test.c | ||
| clk_stm32f.c | ||
| clk_stm32h7.c | ||
| clk_stm32mp1.c | ||
| clk_versal.c | ||
| clk_vexpress_osc.c | ||
| clk_zynq.c | ||
| clk_zynqmp.c | ||
| ics8n3qv01.c | ||
| Kconfig | ||
| Makefile | ||
| mpc83xx_clk.c | ||
| mpc83xx_clk.h | ||