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04b2123b4d
Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
145 lines
3.2 KiB
C
145 lines
3.2 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019, Rick Chen <rick@andestech.com>
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*
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* U-Boot syscon driver for Andes' PLICSW
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* The PLICSW block is an Andes-specific design for software interrupts,
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* contains memory-mapped priority, enable, claim and pending registers
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* similar to RISC-V PLIC.
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*/
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#include <common.h>
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#include <dm.h>
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#include <asm/global_data.h>
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#include <dm/device-internal.h>
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#include <dm/lists.h>
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#include <dm/uclass-internal.h>
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#include <regmap.h>
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#include <syscon.h>
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#include <asm/io.h>
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#include <asm/syscon.h>
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#include <cpu.h>
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#include <linux/err.h>
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/* pending register */
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#define PENDING_REG(base) ((ulong)(base) + 0x1000)
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/* enable register */
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#define ENABLE_REG(base, hart) ((ulong)(base) + 0x2000 + (hart) * 0x80)
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/* claim register */
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#define CLAIM_REG(base, hart) ((ulong)(base) + 0x200004 + (hart) * 0x1000)
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/* priority register */
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#define PRIORITY_REG(base) ((ulong)(base) + PLICSW_PRIORITY_BASE)
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/* Bit 0 of PLIC-SW pending array is hardwired to zero, so we start from bit 1 */
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#define FIRST_AVAILABLE_BIT 0x2
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#define SEND_IPI_TO_HART(hart) (FIRST_AVAILABLE_BIT << (hart))
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#define PLICSW_PRIORITY_BASE 0x4
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#define PLICSW_INTERRUPT_PER_HART 0x1
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DECLARE_GLOBAL_DATA_PTR;
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static int enable_ipi(int hart)
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{
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unsigned int en;
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en = FIRST_AVAILABLE_BIT << hart;
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writel(en, (void __iomem *)ENABLE_REG(gd->arch.plicsw, hart));
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return 0;
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}
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static void init_priority_ipi(int hart_num)
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{
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uint32_t *priority = (void *)PRIORITY_REG(gd->arch.plicsw);
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for (int i = 0; i < hart_num * PLICSW_INTERRUPT_PER_HART; i++) {
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writel(1, &priority[i]);
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}
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return;
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}
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int riscv_init_ipi(void)
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{
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int ret;
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int hart_num = 0;
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long *base = syscon_get_first_range(RISCV_SYSCON_PLICSW);
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ofnode node;
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struct udevice *dev;
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u32 reg;
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if (IS_ERR(base))
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return PTR_ERR(base);
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gd->arch.plicsw = base;
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ret = uclass_find_first_device(UCLASS_CPU, &dev);
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if (ret)
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return ret;
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if (!dev)
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return -ENODEV;
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ofnode_for_each_subnode(node, dev_ofnode(dev->parent)) {
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const char *device_type;
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device_type = ofnode_read_string(node, "device_type");
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if (!device_type)
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continue;
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if (strcmp(device_type, "cpu"))
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continue;
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/* skip if hart is marked as not available */
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if (!ofnode_is_enabled(node))
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continue;
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/* read hart ID of CPU */
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ret = ofnode_read_u32(node, "reg", ®);
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if (ret == 0)
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enable_ipi(reg);
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hart_num++;
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}
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init_priority_ipi(hart_num);
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return 0;
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}
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int riscv_send_ipi(int hart)
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{
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unsigned int ipi = SEND_IPI_TO_HART(hart);
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writel(ipi, (void __iomem *)PENDING_REG(gd->arch.plicsw));
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return 0;
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}
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int riscv_clear_ipi(int hart)
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{
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u32 source_id;
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source_id = readl((void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
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writel(source_id, (void __iomem *)CLAIM_REG(gd->arch.plicsw, hart));
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return 0;
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}
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int riscv_get_ipi(int hart, int *pending)
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{
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unsigned int ipi = SEND_IPI_TO_HART(hart);
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*pending = readl((void __iomem *)PENDING_REG(gd->arch.plicsw));
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*pending = !!(*pending & ipi);
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return 0;
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}
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static const struct udevice_id andes_plicsw_ids[] = {
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{ .compatible = "andestech,plicsw", .data = RISCV_SYSCON_PLICSW },
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{ }
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};
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U_BOOT_DRIVER(andes_plicsw) = {
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.name = "andes_plicsw",
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.id = UCLASS_SYSCON,
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.of_match = andes_plicsw_ids,
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.flags = DM_FLAG_PRE_RELOC,
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};
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