Randolph 04b2123b4d riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy ... Source hart information is not necessary in IPI, so we could use single-bit-per-hart strategy to rearrange PLICSW mapping. Bit 0 of Interrupt Pending Bits is hardwired to 0. Therefore, we use bit 1 to send IPI to hart 0, bit 2 to hart 1, ..., and so on. Signed-off-by: Randolph <randolph@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>		2023-10-19 17:29:33 +08:00
..
aclint_ipi.c	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
andes_plicsw.c	riscv: andes: Rearrange Andes PLICSW to single-bit-per-hart strategy	2023-10-19 17:29:33 +08:00
asm-offsets.c	riscv: Introduce AVAILABLE_HARTS	2022-09-26 14:29:13 +08:00
boot.c	command: Remove the cmd_tbl_t typedef	2020-05-18 18:36:55 -04:00
bootm.c	riscv: bootstage: correct bootstage_report guard	2023-10-04 17:55:17 +08:00
cache.c	common: board_r: support enable_caches for RISC-V	2021-09-07 10:34:29 +08:00
crt0_riscv_efi.S	efi_loader: set IMAGE_FILE_LARGE_ADDRESS_AWARE	2022-12-29 10:51:50 +01:00
elf_riscv32_efi.lds	efi_loader: fix SectionAlignment, FileAlignment	2022-01-15 10:57:22 +01:00
elf_riscv64_efi.lds	efi_loader: fix SectionAlignment, FileAlignment	2022-01-15 10:57:22 +01:00
fdt_fixup.c	fdtdec: Support reserved-memory flags	2021-10-13 14:18:30 -07:00
image.c	riscv: booti: do not force relocation if force_reloc is not set	2021-07-21 16:38:26 +08:00
interrupts.c	arch/riscv: add semihosting support for RISC-V	2022-12-08 15:15:58 +08:00
Makefile	riscv: Rename SiFive CLINT to RISC-V ALINT	2023-07-12 13:21:40 +08:00
memcpy.S	riscv: memcpy: check src and dst before copy	2023-02-01 16:17:45 +08:00
memmove.S	riscv: Fix memmove and optimise memcpy when misalign	2021-05-17 16:47:33 +08:00
memset.S	riscv: assembler versions of memcpy, memmove, memset	2021-04-08 15:37:29 +08:00
reloc_riscv_efi.c	riscv: Remove unused _relocate arguments	2018-07-19 16:31:37 -04:00
reset.c	Revert "riscv: Allow use of reset drivers"	2020-07-24 14:55:31 +08:00
sbi.c	risc-v: implement DBCN write byte	2023-09-05 10:53:55 +08:00
sbi_ipi.c	riscv: Clean up IPI initialization code	2020-07-01 15:01:22 +08:00
semihosting.S	riscv: semihosting: replace inline assembly with assembly file	2023-03-06 19:24:34 -05:00
setjmp.S	riscv: simplify longjmp	2021-04-08 15:37:29 +08:00
sifive_cache.c	riscv: lib: implement enable_caches for sifive cache	2021-09-07 10:34:29 +08:00
smp.c	common: Drop linux/printk.h from common header	2023-09-24 09:54:57 -04:00
spl.c	event: Convert existing spy records to simple	2023-08-31 13:16:54 -04:00