Robert Marko cfb7102d8d arm: mvebu: dts: m801: correct CP1 pinctrl ... Current CP1 pinctrl that is set on the Puzzle M801 is incorrect. CP1 pins are only used for the SMI bus and the MSS I2C, all other pins are just GPIO-s. Due to this being set completely wrong, the pinctrl was actually ended up being hardcoded in the board_early_init_f() step so that SMI would work. That is obviously not the right thing to do, so convert the register hex values that were being written to individual pin modes and set it in the DTS. Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does not get probed without an consumer. Fixes: 2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support") Signed-off-by: Robert Marko <robert.marko@sartura.hr> Reviewed-by: Stefan Roese <sr@denx.de>		2021-10-08 08:37:55 +02:00
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arc	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
arm	arm: mvebu: dts: m801: correct CP1 pinctrl	2021-10-08 08:37:55 +02:00
m68k	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
microblaze	lmb: Switch to generic arch_lmb_reserve_generic()	2021-09-23 14:15:32 -04:00
mips	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
nds32	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
nios2	lmb: nios2: Add arch_lmb_reserve()	2021-09-23 14:15:32 -04:00
powerpc	Convert CONFIG_NAND_FSL_ELBC et al to Kconfig	2021-10-06 09:16:24 -04:00
riscv	riscv: ae350: enable Coherence Manager for ae350	2021-10-07 16:08:23 +08:00
sandbox	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
sh	WS cleanup: remove trailing empty lines	2021-09-30 08:08:56 -04:00
x86	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
xtensa	WS cleanup: remove SPACE(s) followed by TAB	2021-09-30 09:08:16 -04:00
.gitignore
Kconfig	Prepare v2021.10-rc4	2021-09-16 10:29:40 -04:00
u-boot-elf.lds	arch: Add explicit linker script for u-boot-elf	2020-04-03 11:52:55 -04:00